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Compressed Sensing for Wireless Biosignal Monitoring

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The idea is to use CS to compress ECG data.

Short Description

Compressed Sensing (CS) is a signal processing scheme that aims at combining signal acquisition and data compression in one single step and close to the sensor. CS can be implemented very efficiently in digital logic, and the encoding (or compression) step can be performed with very little hardware (and power) effort. Instead, the reconstruction (or decompression) step requires fairly sophisticated algorithms. Understood as data compression/decompression strategy, CS is a highly asymmetric CODEC making its application in low-power wireless telemetry applications, such as wireless body area networks (BAN) for health monitoring.

In a collaboration between the Digital Circuits and Systems group and Analog Mixed Signal group, we have implemented and fabricated an 8-channel biosignal acquisition SoC (System-on-Chip) [1] including analog front-end, analog-to-digital conversion, digital signal processing and a compressed sensing encoder stage.

In this project, we are interested in evaluating the performance of the CS encoder stage in the compression of various types of biosignals. In particular, we will look at ECG (electro-cardio-graphy) signals used to monitor the activity of the heart. We are also interested in finding out whether the CS data can be compressed further by applying entropy encoding on the data obtained from the CS encoder, and what the complexity of a corresponding additional compression stage in hardware would be.

This project may be extended to include the design of a digital ASIC (Application Specific Integrated Circuit) or the implementation in FPGA (Field-Programmable Gate Array).

These are the topics you will deal with:

- Setting-up and measuring practical hardware for biosignal acquisition
- The basics of Compressed Sensing
- The basics of entropy encoding
- Integrated hardware design

Status: Available

Looking for 1 Master student or 2 semester-project students
Supervision: David Bellasi


10% Theory
20% Matlab simulation
20% VLSI or FPGA design
50% Hardware setup and measurements


Matlab, VHDL


Luca Benini