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Counter-based Fast Power Estimation using FPGAs (M/1-3S)

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The power consumed by a digital circuit can be broken down into two main components: leakage power and dynamic power. Dynamic power is proportional to the switching activity of the circuit’s gates. In principle, one could measure dynamic power by observing the switching activity of each single net in the design. This approach is of course completely infeasible as it would need hundreds of gates to track the activity of a single gate, increasing the area of the design by multiple orders of magnitude, along with the number of nets to track.

It has been proven that the activity of a circuit can be closely approximated by randomly selecting a handful of signals to be observed [1]. On the other hand, modern computing systems feature a number of performance counters, i.e. hardware registers tracking carefully selected countable events in the circuit (e.g. cache misses, instruction fetches, floating-point operations, …) with cycle-level accuracy. Performance counters very much reflect the activity of the individual functional units and therefore the whole system. They are usually employed to profile applications performance and resources utilization at runtime; however, studies show they can be very helpful also when it comes to dynamic power modeling, to support both the circuit design phase [2][3] and runtime energy-aware policies [4][5].

Custom designs implemented on FPGAs do not usually come with performance counters, hence it is care of the hardware designer to insert observation points for activity estimation. In this context, an interesting question is whether an approach to hardware counters insertion exist such that activity modeling can be more accurate than random insertion, but less effort than manual performance counters. The implications are very valuable and pave the way for the development of an automatic power modeling framework for any arbitrary netlist, potentially expanding beyond FPGAs.


In this project, you will:

  • devise at least one method to extract the activity of each net in an existing RTL design
  • simulate the power consumption of the implemented design using Xilinx Vivado and/or a state-of-the-art power simulation tool
  • use statistical methods to correlate the toggling activity of a net to the power consumption of the design finding the observation points of interest
  • create a simple performance counter unit to monitor the activity of your ideal set of observation points
  • evaluate your approach.

Depending on the remaining time and your personal interests, further challenges can be tackled:

  • activity of design units usually highly correlate with the activity of unit's databus, which in turn depends on handshaking signals. Expand your approach to detect handshake signals (e.g. ready, valid) and investigate if knowledge about these signals can improve your approach in terms of accuracy and/or runtime
  • implement the design with your performance counter unit on an FPGA and use the data collected to calculate and display the power in real time
  • instead of correlating the activity of the nets to the power of the entire design, correlate it to key design units (like memory, FPU, CPU, ...) and create real-time per-unit power estimates.


  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Interest in power-related topics
  • Preferred: Experience with Xilinx Vivado or any other FPGA toolchain


  • 10% architecture review
  • 20% net activity extraction
  • 30% power simulation
  • 10% implementation
  • 30% evaluation

Project Supervisors