Difference between revisions of "Creating a Free and Open-Source Verification Environment for Our New DMA Engine (1-3S/B)"
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Even though our current verification strategy works, to fully develop the iDMA we need a more capable verification strategy that: | Even though our current verification strategy works, to fully develop the iDMA we need a more capable verification strategy that: | ||
| − | * Only uses free-and-open-source tools (Verilator) to simulate the iDMA | + | * Only uses free-and-open-source tools (Verilator) to simulate the iDMA or uses UVM-based verification elements in QuestaSim |
* Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...) | * Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...) | ||
= Project = | = Project = | ||
| − | In this project, you develop a verification environment around our iDMA Engine | + | In this project, you develop a verification environment around our iDMA Engine. |
== Character == | == Character == | ||
* 30% Planning and design of the test environment | * 30% Planning and design of the test environment | ||
| − | * 50% Implementing a | + | * 50% Implementing a new testbench |
* 20% Verification of / Improving the testbench | * 20% Verification of / Improving the testbench | ||
| Line 42: | Line 43: | ||
* Interest in memory systems | * Interest in memory systems | ||
* Experience with digital design in SystemVerilog as taught in VLSI I | * Experience with digital design in SystemVerilog as taught in VLSI I | ||
| − | * Knowledge of C/C++ | + | * Preferred: Knowledge of C/C++, should Verilator be targetted |
* Preferred: Knowledge of AXI4 | * Preferred: Knowledge of AXI4 | ||
* Preferred: Experience with Verilator | * Preferred: Experience with Verilator | ||
= References = | = References = | ||
Latest revision as of 09:21, 3 November 2023
Contents
Overview
Status: Available
- Type: Bachelor / Semester Thesis or Group Project
- Professor: Prof. Dr. L. Benini
- Supervisors:
Introduction
At IIS we have created a high-performance DMA Engine called iDMA. So far we have verified the unit's correctness using a simple file-based System-Verilog testbench.
Even though our current verification strategy works, to fully develop the iDMA we need a more capable verification strategy that:
- Only uses free-and-open-source tools (Verilator) to simulate the iDMA or uses UVM-based verification elements in QuestaSim
- Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...)
Project
In this project, you develop a verification environment around our iDMA Engine.
Character
- 30% Planning and design of the test environment
- 50% Implementing a new testbench
- 20% Verification of / Improving the testbench
Prerequisites
- Interest in memory systems
- Experience with digital design in SystemVerilog as taught in VLSI I
- Preferred: Knowledge of C/C++, should Verilator be targetted
- Preferred: Knowledge of AXI4
- Preferred: Experience with Verilator
