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Latest revision as of 20:07, 2 August 2022


Overview

Status: Available

Introduction

At IIS we have created a high-performance DMA Engine called iDMA. So far we have verified the unit's correctness using a simple file-based System-Verilog testbench.

Even though our current verification strategy works, to fully develop the iDMA we need a more capable verification strategy that:

  • Only uses free-and-open-source tools (Verilator) to simulate the iDMA
  • Simulates a more realistic memory system (multiple memories, complex latency pattern, reordering, ...)

Project

In this project, you develop a verification environment around our iDMA Engine using Verilator.

Character

  • 30% Planning and design of the test environment
  • 50% Implementing a C++ testbench
  • 20% Verification of / Improving the testbench

Prerequisites

  • Interest in memory systems
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Knowledge of C/C++
  • Preferred: Knowledge of AXI4
  • Preferred: Experience with Verilator

References