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Creating a HDMI Video Interface for PULP

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At the IIS we are developing a platform for parallel ultra low power processing (PULP). It aims at bringing enough processing power at a very narrow power envelope to various IoT devices. Many of the applications are not only meant for machine-machine interfacing but also aim at directly interfacing with humans. Unfortunately at the moment we are lacking any serious user-interfaces and we are constantly falling back to a standard UART (serial) interface.

This is neither very attractive for real world employment of our devices nor is it to demo our cool platform. This thesis would aim at creating such an interface from a hardware point of view.

Project description

On any ASIC implementation we are usually strongly limited by the amount of pins we can spend for a certain interface. This is one of the reasons why we are considering an external HDMI transmitter chip [1] for managing the actual HDMI implementation. In a minimal pin-count configuration it needs 8 data-bits plus some control signals. In contrast to the quite complicated native differential signalling this is easier to implement in a purely digital fashion.

Your task would consist of interfacing such a transmitter and supplying it with data from an on-chip (or external) frame-buffer. At first your implementation will target an FPGA (Xilinz Zynq) implementation as a first prototype but upon successful completion will definitely find its way as an integral part into one of our next generation PULP chips.

Status: Completed

Master thesis of Georg Rutishauser
Supervision: Florian Zaruba, Fabian Schuiki


  • 20% Studying of existing designs
  • 50% RTL Design
  • 30% FPGA Design

In case you are interested in manufacturing your own ASIC as part of this project this topic is suitable for doing so.

Required Skills

  • VHDL or (System)-Verilog knowledge, VLSI I & II


Luca Benini

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Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.