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[[File:StencilMatrix.png|thumb|600px|a) 5- and 9-stencil arrangements, b) resulting matrix structure for least-squares problems.]]
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[[File:StreamingProc.png|thumb|600px|The streaming processor would act as a co-processor for the DMA in the PULP cluster.]]
 
==Short Description==
 
==Short Description==
Linear solvers can be used in many image and video processing applications, e.g. for optical-flow calculation or image domain warping (IDW). In a [http://www.disneyresearch.com/wp-content/uploads/DRAM-or-no-DRAM-Exploring-Linear-Solver-Architectures-for-Image-Domain-Warping-in-28-nm-CMOS-Paper.pdf recent publication] we estimated the area, throughput and power consumption for different solver implementations, and we would now like to verify some of these estimated results using post-layout simulations and ASIC measurements. Besides the verification of these results, we are interested in how well estimation methods at various levels (pre-RTL estimations, gate-level simulations, post-layout simulations) actually match with the measurements of a fabricated ASIC.
 
  
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In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).
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Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability.
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This co-processor could then perform such tasks on-the-fly when the data is being copyied.
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Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression.
  
 
===Status: Available ===
 
===Status: Available ===
 
: Scope: Semester or Master Thesis
 
: Scope: Semester or Master Thesis
 
: Looking for 1-2 Interested Students
 
: Looking for 1-2 Interested Students
: Supervisors: [[:User:kgf|Frank Gürkaynak]], [[:User:schaffner|Michael Schaffner]]
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: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]
  
 
===Prerequisites===
 
===Prerequisites===
 
: VLSI I
 
: VLSI I
: Basic Linear Algebra Course
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: Basic Computer Architecture Course
 
: Matlab, VHDL and C++
 
: Matlab, VHDL and C++
  
 
===Character===
 
===Character===
: 25% Theory & Literature Study
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: 10% Theory & Literature Study
: 25% Evaluations
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: 20% Evaluations
: 50% Hw Architecture & ASIC Implementation
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: 70% Hw Architecture & ASIC Implementation
  
  
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===Partners===
 
===Partners===
: [http://www.disneyresearch.com/research-labs/disney-research-zurich Disney Research Zurich]
 
  
 
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[[#top|↑ top]]
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[[#top|↑ top]]
 
[[#top|↑ top]]
[[Category:Image and Video Processing]] [[Category:Digital]] [[Category:Research]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]]
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[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:2016]]

Revision as of 18:25, 14 April 2016

The streaming processor would act as a co-processor for the DMA in the PULP cluster.

Short Description

In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).

Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. This co-processor could then perform such tasks on-the-fly when the data is being copyied.

Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression.

Status: Available

Scope: Semester or Master Thesis
Looking for 1-2 Interested Students
Supervisors: Michael Schaffner, Michael Gautschi, Antonio Pullini

Prerequisites

VLSI I
Basic Computer Architecture Course
Matlab, VHDL and C++

Character

10% Theory & Literature Study
20% Evaluations
70% Hw Architecture & ASIC Implementation


Professor

Luca Benini

Partners

↑ top

Detailed Task Description

Goals

Practical Details


↑ top