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Difference between revisions of "DMA Streaming Co-processor"

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: Scope: Semester or Master Thesis
 
: Scope: Semester or Master Thesis
 
: Looking for 1-2 Interested Students
 
: Looking for 1-2 Interested Students
: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:gautschi|Michael Gautschi]], [[:User:Pullinia|Antonio Pullini]]
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: Supervisors: [[:User:schaffner|Michael Schaffner]], [[:User:Pullinia|Antonio Pullini]]
  
 
===Prerequisites===
 
===Prerequisites===
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[[#top|↑ top]]
 
[[#top|↑ top]]
[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:Available]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:Processor]] [[Category:2016]]
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[[Category:Digital]] [[Category:Master Thesis]] [[Category:Semester Thesis]] [[Category:ASIC]] [[Category:UlpSoC]] [[Category:PULP]] [[Category:Processor]] [[Category:2016]]

Latest revision as of 09:30, 5 November 2019

Short Description

Sample Preprocessing
The streaming processor would act as a co-processor for the DMA in the PULP cluster.

In many cases a lot of resources are consumed during a preprocessing phase in which the raw data coming, e.g., from an image sensor is transformed in a proper way before being fed to the main processing algorithms. This preprocessing, in many cases, could be done very efficiently while moving the data through the memory hierarchy (e.g. L2 -> L1 transfers).

Like other processors, the PULP platform provides a standard DMA controller for efficient data transfers. In this work, we are going to design a streaming co-processor for the DMA with limited programmability. This co-processor could then perform such tasks on-the-fly when the data is being copied.

Potential application candidates include signal filtering for audio/motion sensor, sub/over sampling, color scheme conversion, image filtering, ciphering and compression/decompression.

Status: Available

Scope: Semester or Master Thesis
Looking for 1-2 Interested Students
Supervisors: Michael Schaffner, Antonio Pullini

Prerequisites

VLSI I
Basic Computer Architecture Course
Matlab, VHDL and C++

Character

20% Theory & Literature Study
30% Evaluations
50% Hw Architecture & ASIC Implementation


Professor

Luca Benini

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Detailed Task Description

Goals

Practical Details


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