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Design and Implementation of Digital Spiking Neurons for Ultra-Low-Power In-Cluster Coprocessors

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Current interest in brain-inspired and neuromorphic computer architectures is enormous, due to its conceptual attractiveness and its potential applications to sensor networks, robotics, low-power vision and other fields. An interesting approach is that followed by the IBM TrueNorth architecture [Merolla14], an homogeneous fabric of 1 million digital spiking neurons that can be used for visual classification at a very low power budget (65 mW). Tight integration of digital spiking neurons with other kinds of low-power computers is a totally unexplored field. This project aims at enabling its exploration with the development of spiking neural coprocessors to be integrated into an ultra-low-power computing cluster composed of fully programmable RISC cores and traditional coprocessors/accelerators.

Goal of the Project

he project is structured in consecutive steps; the first step is to design a digital spiking neuron based/inspired on the TrueNorth neuron [Cassidy13] and use it to build a small spiking neural network coprocessor to be integrated with the PULP ultra-low-power platform. After verifying correct functionality, you will integrate the complete accelerator inside the PULP platform (either in the simulation platform or the FPGA emulation platform).

Outcomes and Acquired Expertise

With this project you will work in a field of active exciting research to develop a state-of-art neuromorphic accelerator for MPSoC and FPGA targets. You will learn:

  • how to design a hardware module and integrate it within a more complex platform, using EDA tools for verification and RTL synthesis to evaluate results;
  • how spiking neural networks models work and how they differ from other neural models

Required Skills

To work on this project, you will need:

  • a minimum level of confidence with basic engineering tools (web search, basic usage of Linux operating system, compilers…) and of work independence
  • to have worked in the past with at least one RTL language (SystemVerilog or Verilog or VHDL)
  • to have basic prior knowedge of hardware design and computer architecture (i.e. have followed the relative courses)

Other skills that you might find useful include:

  • basic familiarity with a scripting language for numerical simulation (Python or Matlab or Lua…)
  • to be strongly motivated for a difficult but super-cool project

If you want to work on this project, but you think that you do not match some the required skills, we can give you some preliminary exercise to help you fill in the gap.

Status: Completed

Sharan Kumaar Ganesan (KTH Stockholm)

Supervision: Francesco Conti
Date: 9/2016


Luca Benini

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Detailed Task Description

Meetings & Presentations

The students and advisor(s) agree on weekly meetings to discuss all relevant decisions and decide on how to proceed. Of course, additional meetings can be organized to address urgent issues.

Around the middle of the project there is a design review, where senior members of the lab review your work (bring all the relevant information, such as prelim. specifications, block diagrams, synthesis reports, testing strategy, ...) to make sure everything is on track and decide whether further support is necessary. They also make the definite decision on whether the chip is actually manufactured (no reason to worry, if the project is on track) and whether more chip area, a different package, ... is provided. For more details confer to [1].

At the end of the project, you have to present/defend your work during a 15 min. presentation and 5 min. of discussion as part of the IIS colloquium.


  • [Cassidy13] A. S. Cassidy et al., “Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores,” in The 2013 International Joint Conference on Neural Networks (IJCNN), 2013, pp. 1–10.
  • [Merolla14] P. A. Merolla et al., “A million spiking-neuron integrated circuit with a scalable communication network and interface,” Science, vol. 345, no. 6197, pp. 668–673, Aug. 2014.

Practical Details


  • The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [2]
  • The IIS/DZ coding guidelines [3]

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