Information for "Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA"
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Basic information
| Display title | Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA |
| Default sort key | Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA |
| Page length (in bytes) | 4,841 |
| Page ID | 28 |
| Page content language | English (en) |
| Page content model | wikitext |
| Indexing by robots | Allowed |
| Number of redirects to this page | 1 |
| Counted as a content page | Yes |
Page protection
| Edit | Allow all users (infinite) |
| Move | Allow all users (infinite) |
Edit history
| Page creator | Kgf (talk | contribs) |
| Date of page creation | 17:18, 16 January 2014 |
| Latest editor | Weberbe (talk | contribs) |
| Date of latest edit | 10:43, 6 November 2017 |
| Total number of edits | 20 |
| Total number of distinct authors | 3 |
| Recent number of edits (within past 90 days) | 0 |
| Recent number of distinct authors | 0 |
