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In this thesis, the clever student will implement the first ever hardware realization of the LEG-CVA. The designed ASIC will have a smart architecture implemented in VHDL and an efficient back-end design. Finally, the low-power efficient ASIC design can be fabricated in state-of-the-art CMOS technology.
 
In this thesis, the clever student will implement the first ever hardware realization of the LEG-CVA. The designed ASIC will have a smart architecture implemented in VHDL and an efficient back-end design. Finally, the low-power efficient ASIC design can be fabricated in state-of-the-art CMOS technology.
 
===Status: Available ===
 
: Looking for 1-2 Semester/Master students
 
: Contact: [[:User:Badawi|Karim Badawi]]
 
 
===Prerequisites===
 
: VLSI I
 
: Interest in Mobile Communications
 
: Matlab and VHDL knowledge
 
  
 
<!--  
 
<!--  
Line 21: Line 12:
 
: Matthias Baer, Renzo Andri
 
: Matthias Baer, Renzo Andri
 
--->
 
--->
<!--
 
 
===Status: In Progress ===
 
===Status: In Progress ===
: Student A, StudentB
+
: Student: Andreas Kurth
: Supervision: [[:User:Badawi Karim Badawi]]
+
: Supervision: [[:User:Badawi|Karim Badawi]], [[:User:Weberbe|Benjamin Weber]]
--->
 
===Character===
 
: 15% Theory/Algorithm
 
: 60% Architecture/VHDL
 
: 25% ASIC Implementation
 
  
 
===Professor===
 
===Professor===
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] --->
 
 
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
 
==Detailed Task Description==
 
 
===Goals===
 
===Practical Details===
 
* '''[[Project Plan]]'''
 
* '''[[Project Meetings]]'''
 
* '''[[Design Review]]'''
 
* '''[[Coding Guidelines]]'''
 
* '''[[Final Report]]'''
 
* '''[[Final Presentation]]'''
 
 
==Results==
 
  
==Links==
 
 
[[Category:Digital]]
 
[[Category:Digital]]
 
[[Category:In progress]]
 
[[Category:In progress]]
 
[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
[[Category:Master Thesis]]
+
[[Category:ASIC]]
 +
[[Category:Telecommunications]]
 +
[[Category:Weberbe]]
 +
[[Category:Badawi]]
  
[[#top|↑ top]]
 
  
 
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GROUP
 
GROUP
 
[[Category:Digital]]
 
[[Category:Digital]]
 +
    SUB CATEGORIES
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    [[Category:ASIC]]
 +
    [[Category:FPGA]]
 +
    [[Category:Cryptography]]
 +
    [[Category:System Design]]
 +
    [[Category:Processor]]
 +
    [[Category:Telecommunications]]
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    [[Category:System Design]]
 +
    [[Category:Modelling]]
 +
 +
 
[[Category:Analog]]
 
[[Category:Analog]]
[[Category:TCAD]]
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[[Category:Nano-TCAD]]
[[Category:Nano Electronic]]
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[[Category:Nano Electronics]]
  
 
STATUS
 
STATUS
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[[Category:In progress]]
 
[[Category:In progress]]
 
[[Category:Completed]]
 
[[Category:Completed]]
[[Category:Research]]
 
 
[[Category:Hot]]
 
[[Category:Hot]]
  
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[[Category:Master Thesis]]
 
[[Category:Master Thesis]]
 
[[Category:PhD Thesis]]
 
[[Category:PhD Thesis]]
 +
[[Category:Research]]
  
 
NAMES OF EU/CTI/NT PROJECTS
 
NAMES OF EU/CTI/NT PROJECTS
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[[Category:PSocrates]]
 
[[Category:PSocrates]]
 
[[Category:UlpSoC]]
 
[[Category:UlpSoC]]
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[[Category:Qcrypt]]
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[[Category:PULP]]
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[[Category:ArmaSuisse]]
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 +
YEAR (IF FINISHED)
 +
[[Category:2010]]
 +
[[Category:2011]]
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[[Category:2012]]
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[[Category:2013]]
 +
[[Category:2014]]
 +
[[Category:2015]]
 +
 
--->
 
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Revision as of 18:35, 5 February 2015

First ASIC Realization for a new HSPA.jpg

Short Description

High Speed Packet Access (HSPA) is the fastest growing wireless technology. HSPA+ provides an evolution of HSPA and offers data rates up to 168 Megabits per second (Mbit/s) to the mobile device and 22 Mbit/s from the mobile device. HSPA+ upgrades the existing 3G network and provides a cheap way for telecom operators to migrate towards 4G speeds without deploying a new radio interface, instead of the expensive conversion to the Long-Term Evolution (LTE). This makes HSPA/HSPA+ the dominant future wireless technology.

In order to bring this to practice, clever Multiuser detection and equalization techniques have to be deployed at the UE. At the IIS, we have just invented an excellent novel linear equalization and progressive grouping-assisted constrained Viterbi algorithm (LEG-CVA) as a near-maximum likelihood sequence estimation (MLSE) approach for the downlink.

In this thesis, the clever student will implement the first ever hardware realization of the LEG-CVA. The designed ASIC will have a smart architecture implemented in VHDL and an efficient back-end design. Finally, the low-power efficient ASIC design can be fabricated in state-of-the-art CMOS technology.

Status: In Progress

Student: Andreas Kurth
Supervision: Karim Badawi, Benjamin Weber

Professor

Qiuting Huang