Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
High Speed Packet Access (HSPA) is the fastest growing wireless technology. HSPA+ provides an evolution of HSPA and offers data rates up to 168 Megabits per second (Mbit/s) to the mobile device and 22 Mbit/s from the mobile device. HSPA+ upgrades the existing 3G network and provides a cheap way for telecom operators to migrate towards 4G speeds without deploying a new radio interface, instead of the expensive conversion to the Long-Term Evolution (LTE). This makes HSPA/HSPA+ the dominant future wireless technology.
In order to bring this to practice, clever Multiuser detection and equalization techniques have to be deployed at the UE. At the IIS, we have just invented an excellent novel linear equalization and progressive grouping-assisted constrained Viterbi algorithm (LEG-CVA) as a near-maximum likelihood sequence estimation (MLSE) approach for the downlink.
In this thesis, the clever student will implement the first ever hardware realization of the LEG-CVA. The designed ASIC will have a smart architecture implemented in VHDL and an efficient back-end design. Finally, the low-power efficient ASIC design can be fabricated in state-of-the-art CMOS technology.