Design and VLSI Implementation of a Constrained-Viterbi Algorithm Equalizer for 3GPP TD-HSPA
TD-HSPA is a 3GPP standard that combines an advanced TDMA/TDD system with an adap- tive CDMA component operating in a synchronous mode. Its TDD nature allows to master asymmetric services more efficiently than other 3G standards. Up- and downlink resources are flexibly assigned according to traffic needs, and a flexible data rate is provided. That is helpful in an environment with increasing data traffic, which tends to be asymmetric (mobile Internet). In order to bring this to practice, clever multiuser detection and equalization techniques have to be deployed at the UE. To this end, we have developed a high-performance low-complexity joint multiuser sequence detection algorithm.
The aim of this project is the design of a hardware architecture and VLSI implementation of a constrained Viterbi algorithm as part of a bigger sequence estimation algorithm for joint multiuser detection in TD-HSPA systems. Therefore, the Viterbi-based Maximum Likelihood Sequence Detection (MLSD) is the optimal detection technique in a multipath propagation environment, however, the realization of the MLSD algorithm in an environment such as that of the TD-HSPA standard (deploying higher-order modulation up-to 64-QAM and multiplexing of up-to 16 users over the same physical channel in the presence of several multipath components) is not feasible due to prohibitive complexity. This is due to the fact that the complexity of the optimal MLSD algorithm grows exponentially with the constellation size, the number of users and the number of multipath components exhibited by the wireless channel, which renders the MLSD computation for a system with such dimensions practically impossible given the current power, speed and complexity constraints.
Therefore, in a previous research work, we have targeted designing a near-MLSD algorithm referred as Linear Equalization and Group Detection-assisted Constrained Viterbi Algorithm (LEG-CVA). LEG-CVA is a two-step algorithm; namely, a preprocessor and a constrained Viterbi equalizer. A high-level block diagram of the algorithm is shown in Fig. 1. In the preprocessing step, the minimum mean squared-error linear equalizer (MMSE-LE) resolves the inter-symbol interference (ISI) resulting from the dispersive channel, approximately removing the time dependency between consecutive symbols and reducing the effective channel memory. Afterwards, the users in the system are divided into groups, where MLD is applied to the in- dividual groups treating the multiple-access interference (MAI) due to users in other groups as colored noise. Starting with one user per group, the number of users in each group gradually increases until there is only one group having all the users in the system. The progressive group- ing is explained in more details in . The preprocessing step is concluded with deciding over a number of candidate values (for each transmit super-symbol) that are deemed most probable according to the MLD criterion. The number of users per group and the corresponding number of surviving candidate values are considered design-specific parameters and will be assumed constant for the purposes of this design project.
In the second step of the LEG-CVA, a Viterbi equalizer is run considering only the set of surviving group candidates from the previous step. After the preprocessing step, U -candidates that survived the last stage of the progressive group detection with the ISI effects being isolated by the MMSE-LE are reached. These surviving candidates constitute the trellis states in the CVA at the respective time instant. The reduced-state Viterbi equalizer decides on the best sequence of super-symbols that minimizes the symbol-error-rate given the constrained set. This step concludes the hard-output LEG-CVA.
- Student: Andreas Kurth (sem14h9)
- Supervision: Karim Badawi, Benjamin Weber
- Year: 2015
- Chip gallery page of XinGe
 Karim Badawi, Christian Benkeser, Christoph Roth, Qiuting Huang, Andreas Burg. A Novel Constrained-Viterbi Algorithm with Linear Equalization and Grouping Assistance. In IEEE International Symposium on Wireless Communication Systems (ISWCS), pages 231-235, September 2012. DOI: 10.1109/ISWCS.2012.6328364