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Design of a CAN Interface to Enable Reliable Sensors-to-Processors Communication for Automotive-oriented Embedded Applications (1M)

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This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.

Status: Available

Project Description and Objectives

Modern embedded systems that run real-time applications require reliable protocols to enable the communications between sensors, actuators, controllers and other nodes. The controller Area Network (CAN) bus is a robust serial bus communications protocol that meet these requirements and allows microcontrollers and devices to communicate with each other's applications without a host computer. Initially specified and developed by Bosch in the early 1980s, this protocol is widely used today in industrial automation and other areas of networked embedded control, with applications in diverse products such as combustion and electric vehicles, agriculture, aviation and navigation electronics, elevators, medical instruments, railways applications, 3d printers..

The CAN bus is a message-based protocol, designed originally for multiplexing electrical wiring within automobiles to save on copper. For each device, the data in a frame is transmitted serially but in such a way that if more than one device transmits at the same time, the highest priority device can continue while the others back off. Frames are received by all devices, including by the transmitting device. More information can be found in [1].

This project aims to extend the I/O peripherals of a Linux-capable RISC-V SoC processor with a novel designed CAN interface.

Technical Activities

To achieve the project's goals, the student is required to complete the following activities:

  • Study the CAN protocol and existing implementations;
  • Design the CAN interface IP in SystemVerilog;
  • Integrate the peripheral into a full SoC system;
  • Verify the functionality of the IP through custom test-benches and available Linux-drivers;

Weekly Reports

The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.

Learning Opportunities

The student will gain advanced knowledge on I/O SoC communication, from hardware and firmware perspectives. The student will work in a team of PhDs and post-doc researchers and will be fully supported along the entire duration of the project. Moreover, the student will practice with commercial tools for hardware design.


  • 20% Study state-of-the-art and existing implementations of the IP;
  • 40% Hardware design;
  • 15% Functional Verification;
  • 20% Evaluation and Documentation;
  • 5% Final Report.


  • Interest in deepening system I/O communication topics
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Good knowledge of C and Assembly
  • Experience with Unix commands
  • Preferred: Experience with bash scripting
  • Preferred (not strictly required): Knowledge of the AXI4 protocol


[1] CAN Bus: