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Design of a Prototype Chip with Interleaved Memory and Network-on-Chip

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Status: Completed


As the number of compute cores and accelerators on a single chip is rapidly growing, there is a rising need for scalable, high-bandwidth and low-latency on-chip commu- nication fabrics. This need is often addressed by deploying networks-on-chip (NoCs) through which the compute cores can communicate similar to how computers can communicate through the Internet. These NoCs can occupy a significant percentage of the total chip area and as the number of cores on a single chip increases, this percentage keeps increasing. In contrast to compute cores that reach a high logic cell utilization, the part of the chip where the NoC sits usually attains a rather low cell utilization since NoCs are dominated by routing. We could take advantage of the otherwise unused regions of the chip where the NoC sits by instantiating a latch-based standard-cell memory (SCM) as a scratchpad memory (SPM) directly addressable by the NoC.


The goal of this thesis is to develop a prototype that interleaves SCM (which is dominated by logic cells) and the NoC (which is dominated by routing) in order to maximize the utilization of both logic cells and routing. The thesis should explore the benefit of memory-in-NoC by showing how much additional memory we can add without significantly increasing the total chip area.


  • 30% Architecture Specification
  • 40% Implementation of the architecture
  • 30% SCM in NoC exploration


  • Experience with the System Verilog language, VLSI 1
  • Experience with physical implementation, VLSI 2