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(Created page with "<!-- Design of a Reconfigurable Vector Processor Cluster for Area Efficient Radar Processing (1M) --> Category:Digital Category:High Performance SoCs Category:Comp...")
 
 
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* Supervisors:
 
* Supervisors:
 
** [[:User:Agarofalo | Angelo Garofalo]]: [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]
 
** [[:User:Agarofalo | Angelo Garofalo]]: [mailto:agarofalo@iis.ee.ethz.ch agarofalo@iis.ee.ethz.ch]
 +
** [[:User:Mperotti | Matteo Perotti]]: [mailto:mperotti@iis.ee.ethz.ch mperotti@iis.ee.ethz.ch]
 
** [[:User:Matheusd | Matheus Cavalcante]]: [mailto:matheusd@iis.ee.ethz.ch matheusd@iis.ee.ethz.ch]
 
** [[:User:Matheusd | Matheus Cavalcante]]: [mailto:matheusd@iis.ee.ethz.ch matheusd@iis.ee.ethz.ch]
  

Latest revision as of 19:42, 22 November 2022


Overview

The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal processing.

Status: Available

Project Description and Objectives

Processing data from RADARs is a fundamental task to be performed in autonomous driving automotive applications but also in civil aviation, weather and many other applications. The operations to be performed are very heterogeneous, mixing control and compute-intensive tasks. Vector architectures are suitable to sustain compute-intensive workloads at high performance and energy efficiency, whereas general-purpose cores can handle control-oriented and I/O operations. However, integrating vector units and scalar processors into a heterogeneous fabric is very expensive in terms of area and power budget, especially when we consider embedded systems mounted on a car, for example. Reconfigurable hardware architectures are attractive since they can meet the performance and power objectives at a reduced area footprint, still offering high flexibility: hardware compute units can be re-configured (possibly via software) to act as general-purpose or specialized processing engines.

The aim of this project is to design a reconfigurable vector processor cluster for area-optimized, yet compute and energy-efficient, radar signal processing. The vector cluster will operate either in scalar or vector mode and will efficiently sustain control tasks as well as compute-intensive vectorial workloads.

Technical Activities

To achieve the project's goals, the student is required to complete the following activities:

  • Identify state-of-the-art RADAR processing applications;
  • Implement the applications on a reference multi-core scalar RISC-V processor and analyze performance and energy metrics as well as compute and memory bottlenecks;
  • Design and synthesize the reconfigurable vector processor cluster to optimize area footprint of the system;
  • Benchmark the system on the previously identified application and perform additional optimizations to meet the performance requirements;
  • (Very Advanced, optional) Physically implement the system targeting a leading-edge technology node to fully characterize the system.

Weekly Reports

The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.

Learning Opportunities

The student will gain advanced knowledge on vector processors, RADAR signal processing and on reconfigurable architectures. The student will work on an advanced research topic, within a team of PhDs and post-doc researchers that will support the student in all the project phases. Moreover, the student will practice with most common commercial tools used for hardware design.

Character

  • 20% state-of-the-art review
  • 50% hardware design
  • (20)- 25% Functional testing and evaluation
  • (5%) physical implementation (under close guidance, optional)
  • 5% Final report


Prerequisites

  • Strong interest for automotive applications, radar signal processing and vectorial architectures
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Good knowledge of C and Assembly
  • Experience with Unix commands
  • Preferred: Experience with bash scripting
  • Preferred (not strictly required): Experience with ASIC implementation flow (synthesis) as taught in VLSI II


References

[1] https://ieeexplore.ieee.org/abstract/document/9369027

[2] M. Cavalcante, F. Schuiki, F. Zaruba, M. Schaffner, and L. Benini, "Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with multiprecision floating-point support in 22nm FD-SOI," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 28, no. 2, pp. 530–543, 2020.

[3] https://arxiv.org/abs/2207.07970