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Design of a Scalable High-Performance and Low-Power Interface Based on the I3C Protocol (1M)

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Overview

This project aims to design a low-power, high-performance, scalable and area-optimized I3C peripheral that adheres to the specifications by MIPI Alliance.

Status: Available

Project Description and Objectives

As smart phones, wearables, IoT (Internet of Things) devices, systems in automobiles and server environments become more advanced and complex, the necessity for more streamlined, high performance, scalable and cost-effective communication interfaces are required to control and transmit data with high speeds, in energy-saving and space-saving designs.

I2C and SPI have long been the primary interface choice for embedded devices. While these interfaces are relatively simple to implement and have been widely adopted over the years, they both lack some critical features and have limitations. This applies especially for deeply-embedded applications, which can significantly impact designing densely packed systems.

I3C (Improved-Inter Integrated Circuit) aims both to fix the limitations of legacy interfaces (I2C and SPI) and to also add other enhancements. I3C specification developed by MIPI Alliance [1] , is an intelligent multi-featured interface that improves upon the key attributes of traditional I2C and SPI interfaces to provide a new, unified, and high-performing solution. I3C is a serial communication interface implemented using a complementary metal oxide semiconductor (CMOS) I/O, which uses a two-wire interface to minimize pin counts and number of signal paths between components. It enables the use of higher bandwidth operating modes at very low power levels and allows simpler, yet more flexible design implementation. The I3C standard is designed to retain some backward compatibility with the I²C system, notably allowing designs where existing I²C devices can be connected to an I3C bus, but still supports the ability to switch to a higher data rate for communication at higher speeds between compliant I3C devices.

This project aims to design a low-power, high-performance, scalable and area-optimized I3C peripheral that adheres to the specifications by MIPI Alliance. The functionality of the peripheral will be tested through a set of custom test-benches, (following the UVM methodology [4] if the student is interested in this topic). Eventually, the project can be completed with the integration of the designed peripheral into a full SoC system that runs Linux [2]. To this extent, system-level integration, verification and evaluation must be performed as well as the design of the Linux drivers for the I3C peripheral.

Technical Activities

To achieve the project's goals, the student is required to complete the following activities:

  • Study and Analysis of the I3C communication protocol;
  • Design and implementation of the I3C I/O peripheral;
  • Design of test-benches for functional verification (possibly using UVM structure);
  • (Advanced, optional) Integration of the IP within a Linux-capable full SoC system;
  • (Very advanced, optional) Design and Integration of I3C drivers within the Linux kernels;

Weekly Reports

The student is required to write a weekly report at the end of each week and send it to his advisors by email. The weekly report aims to briefly summarize the work, progress, and any findings made during the week, plan the actions for the next week, and discuss open questions and points. For software programming benchmarks, we strongly recommend creating a google-sheet and plotting the results to trace your benchmark results.

Learning Opportunities

The student will gain advanced knowledge on I/O SoC communication from hardware and firmware perspectives. The student will work in a team of PhDs and post-doc researchers and will be fully supported along the entire duration of the project. Moreover, the student will practice with commercial tools for hardware design.

Character

  • 10% State-of-the-art review
  • (45-) 55% Hardware Design
  • 20% Functional Testing
  • (5-) 10% Evaluation and Documentation
  • 5% Final Report
  • (Optional, very advanced) 10% Firmware Design


Prerequisites

  • Interest in deepening system I/O communication topics
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Good knowledge of C and Assembly
  • Experience with Unix commands
  • Preferred: Experience with bash scripting
  • Preferred (not strictly required): Knowledge of the AXI4 protocol


References

[1] MIPI Alliance Specification for I3C® (Improved Inter Integrated Circuit), version 1.1.1, MIPI Alliance, Inc., 11 June 2021.

[2] Ariane, RISC-V application processor: https://ieeexplore.ieee.org/abstract/document/8777130

[3] MIPI Alliance “Introduction to the MIPI I3C Standardized Sensor Interface”, August 2016

[4] https://learnuvmverification.com/