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==Short Description==
 
==Short Description==
  

Revision as of 14:35, 1 October 2014

LTE module.png

Short Description

Various estimates predict 20 to 30 billion embedded devices connected to the internet in 2020 in what’s called the the Internet of things (IoT). To realize this vision, cellular standards are released to meet the requirements regarding low-power and low-cost of IoT components, especially on the client side. In the latest release of the LTE standard, a new user-equipment category (Cat-0) for Machine to Machine (M2M) communications and the Internet of things (IoT) was introduced [1].

The goal of this project is, to design a Physical Layer modem, whereas a state-of-the-art LTE transceiver [2] can be used. You will start your design by doing a system analysis on the required building blocks (Synchronization, FFT, Symbol detection, etc.). Then adapt and extend the existing LTE framework towards Category 0 devices. In a second stage implement the design on an FPGA attached to the LTE transceiver.


Status: Available

Looking for Interested Students
Supervision: Harald Kröll, Benjamin Weber

Character

50% Theory/Matlab
50% FPGA Design

Prerequisites

VLSI I
Matlab, VHDL

Professor

Qiuting Huang


Links

[1] http://www.nextgcom.co.uk/wordpress/wp-content/uploads/2014/09/ARM-NextG-LTE-Cat0-White-Paper-Final.pdf

[2] http://www.newacp.ch/products/4g-lte-enabled-transceivers/↑ top