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[[Category:Semester Thesis]]
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= Overview =
= Overview =

Revision as of 14:22, 4 January 2022


Status: Available

  • Type: Semester Thesis
  • Professor: Prof. Dr. L. Benini
  • Supervisors:


Current PULP SoCs are the state of the art in terms of energy efficiency in active mode. With various low-power techniques implemented in the form of optimized cores, dedicated hardware accelerators our SoCs excel at dynamic power usage. However, most modern MCUs require strong deep sleep capabilities which are the key aspect in heavily duty-cycled applications which enable IO-devices to operate for months from a single coin-cell battery. Although all of our PULP chips consist predominantly of open-source hardware we currently have to (if at all) rely on proprietary power management solutions to power gate the SoC.


The goal of this project is to develop a parametric power management unit for PULP systems to bring our SoC to the next level in terms of deep sleep power consumption. As part of the thesis you will deepen your skills in SystemVerilog development and couple them with a deep dive into power planning and backend design. The ultimate goal of this project would be to tape-out your very own PULP SoC with modular power gating capabilities using modern, industry-standard EDA tools for IC design.

  • Review and get familiar with existing PULP SoC Architecture
  • Read up on design flows for power planning in SoC (UPF standard)
  • Invent and Implement configurable and parametrizable PMU in SystemVerilog
  • Implement power specification for PULP SoC in a modular fashion
  • Design PULP ASIC with modular power gating capabilities controlled by new PMU
  • Simulate potential power saving potential for different application scenarios'

Depending on your preferences and prior experience, you may choose to focus only on parts of the overall project, work in a team (prefered option in case of semester thesis).


  • 20% Literature / architecture review
  • 20% RTL implementation
  • 40% Power Plannign & Backend Design
  • 20% Evaluation/Simulation


  • Strong interest in computer architecture and SoCs
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Experience with ASIC implementation flow (ASIC Backend/power-planning flow) as taught in VLSI II (the project can be started in parallel to attending the VLSI2 lecture)
  • Basic Linux OS handling skills