View source for Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M)

<!-- Designing a Scalable Miniature I/O DMA (1-2B/1-3S/M) -->

[[Category:Digital]]
[[Category:High Performance SoCs]]
[[Category:Computer Architecture]]
[[Category:2023]]
[[Category:Semester Thesis]]
[[Category:Bachelor Thesis]]
[[Category:Master Thesis]]
[[Category:Tbenz]]
[[Category:Michaero]]
[[Category:In progress]]


= Overview =

== Status: In Progress ==

* Type: Bachelor / Semester / Master Thesis
* Professor: Prof. Dr. L. Benini
* Supervisors:
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]
** [[:User:Michaero | Michael Rogenmoser]]: [mailto:michaero@iis.ee.ethz.ch michaero@iis.ee.ethz.ch]

= Introduction =

At IIS we are developing an architectural family of lightweight yet high-performance data movement engines (iDMA)[1].

Furthermore, our PULPissimo systems use a different DMA architecture (uDMA [2]), specifically designed to interact with SoC peripherals.

= Project =

The goal of this project is to replace the internal data movement component within the uDMA with the iDMA, simplifying the code base within the design.

Depending on the progress, this project could result in a Tapeout.

== Character ==

* 40% RTL Design and Verification
* 20% Software / Driver / HAL writing (C)
* 40% Evaluation


== Prerequisites ==

* Experience with digital design in SystemVerilog as taught in VLSI I

= References =

* [1] https://github.com/pulp-platform/iDMA
* [2] https://github.com/pulp-platform/udma_core