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Difference between revisions of "Digital Audio High Level Synthesis for FPGAs"

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#REDIRECT [[Digital Audio Processor for Cellular Applications]]
 
 
==Short Description==
 
Research and development departments are often facing the challenge of minimizing product time to market and at the same time maintaining high product quality. High Level Synthesis (HLS) tools such as [1], which synthesize high level programming code (C/C++) to an FPGA bit stream, can be used to combat this conflict. In particular if reference implementations in a high level programming language or simulation models already exist, the tedious steps from mapping the high level implementation to RTL code can be omitted.
 
 
 
In this project, 3GPP mobile communication voice codec reference implementations such as [2] shall be synthesized to FPGA using industrial HLS tools. The results can be demonstrated on a mobile tester platform developed at the IIS. Then, a manually created RTL version of the same voice codec shall be implemented. Eventually, the HLS and RTL versions can be compared with respect to power consumption, area requirements, and more.
 
 
 
===Status: Available ===
 
: Looking for 1-2 Semester/Master students
 
: Contact: [[:User:Weberbe|Benjamin Weber]]
 
 
 
===Prerequisites===
 
: Interest in mobile communication
 
 
 
===Character===
 
: 20% Theory
 
: 80% Implementation
 
 
 
===Professor===
 
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
 
 
==References==
 
 
 
[1] [http://www.xilinx.com/products/design-tools/vivado/integration/esl-design/ XILINX High Level Synthesis]
 
 
 
[2] [http://www.3gpp.org/DynaReport/46053.htm EFR Speech Codec Reference Implementation]
 
 
 
[[Category:Digital]]
 
[[Category:Available]]
 
[[Category:Semester Thesis]]
 
[[Category:Master Thesis]]
 
[[Category:Telecommunications]]
 
[[Category:FPGA]]
 
[[Category:Audio]]
 
[[Category:Weberbe]]
 

Latest revision as of 15:36, 3 August 2015