Difference between revisions of "Digital Beamforming for Ultrasound Imaging"
From iis-projects
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===Status: Available === | ===Status: Available === | ||
: Looking for Interested Students | : Looking for Interested Students | ||
− | : Supervision: [[:User: | + | : Supervision: [[:User:Phager|Pascal Hager]], [[:User:vogelpi|Pirmin Vogel]] |
===Character=== | ===Character=== |
Revision as of 19:20, 24 March 2015
Short Description
Ultrasound imaging is an important biomedical technique for analyzing soft tissues in the human body, with both diagnostic and therapeutic applications. IIS is involved in a project developing a high-performance, portable 3D ultrasound platform.
The basic principle of ultrasound imaging is to excite the target body with high-frequency acoustic pulses and to form an image using the back-reflected echoes. The reconstruction of the image based on these echoes is called beamforming and for today's 2D transducer heads with several thousand transducer elements, it is definitely the computationally most intensive operation. In order to allow for portable 3D ultrasound systems, new algorithms and hardware architectures for digital beamforming are currently being developed at IIS.
The goal of this semester project is the optimization and ASIC implementation of a few processing channels of a beamformer for ultrasound imaging. In order to do an accurate design feasibility study of the complete beamformer architecture, the fabricated ASIC is tested, measured and physically characterized in a second phase.
Alternatively, depending on the students interest, an FPGA implementation is also possible.
Depending on the choosen platform (ASIC/FPGA) the work either targets ...
- ... a high-frame rate (>1000Hz) synthetic aperture beamformer (FPGA)
- ... a low-power software configurable 2D receive beamformer (ASIC)
This project is sponsored by UltrasoundToGo Nano-Tera Project
Status: Available
- Looking for Interested Students
- Supervision: Pascal Hager, Pirmin Vogel
Character
- 20% Theory, Algorithms and Simulation
- 40% VHDL
- 40% ASIC/FPGA Design
Prerequisites
- VLSI I
- Matlab, VHDL