Digital Transmitter for Cellular IoT
By the end of the decade billions so called Internet-of-Things (IoT) devices will be connected to the Internet. IoT nodes can range from electrical energy meters to tiny positioning nodes connected to a network. While legacy 2G GPRS has long been used for cellular IoT (cIoT) applications, recent advancements in the 3GPP standardization organization address the growing need for IoT modems. In particular, Extended Coverage GSM (EC-GSM) with 20 dB coverage increase and low-power features is likely to be introduced in March 2016 .
A complete GSM/GPRS/EDGE/Evolved EDGE physical layer is available at IIS from the razorEDGE and stoneEDGE projects. However, both project have no EC-GSM support and EC-GSM development has just begun. The goal of this project is to design a generic digital transmitter that accepts bits and configuration data from layer 2. It interleaves, encodes, punctures, and modulates the bits. The digital transmitter transfers the modulated bits to a DAC within an RF frontend. The transmitter should be versatile enough to support legacy GSM, GPRS, EDGE, and Evolved EDGE but also EC-GSM for cIoT. Furthermore, the transmitter should be generic enough that it is possible to e.g. turn off Evolved EDGE support before synthesis in order to save silicon area if Evolved EDGE is not required. The transmitter will eventually replace the transmitter in the existing stoneEDGE physical layer ASIC. There exists an FPGA based testbed which uses an ML605 FPGA board from Xilinx  and an evalEDGE RF board. The testbed can be used for fast prototyping. This project will involve modelling in Matlab but mostly it is HDL design, synthesis, and FPGA testing.
This project is a perfect opportunity to apply architectural design methods. The outcome is likely to be the first EC-GSM capable transmitter implementation worldwide (except for software defined prototypes).
- Looking for interested students (Semester or Master Thesis)
- Supervision: Benjamin Weber
- 20% Theory
- 40% Architecture Design
- 40% HDL Implementation
- VLSI I
 Cellular system support for ultra-low complexity and low throughput Internet of Things (CIoT), 3GPP TR 45.820 v13.1.0, 2015.
 Virtex-6 FPGA ML605 Evaluation Kit, http://www.xilinx.com/products/boards-and-kits/ek-v6-ml605-g.html, Dec 2015.