Difference between revisions of "Digital Transmitter for Mobile Communications"
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[[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]] | [[File:Creating Transmitter and Testbed Development for TD-SCDMA.jpg|thumb|300px]] | ||
==Short Description== | ==Short Description== | ||
| − | In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the receiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. The | + | In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the receiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. |
| + | The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver. | ||
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| + | The goal of this project is to design the digital transmitter and implement it either as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and finally measured during the VLSI III lecture. | ||
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===Status: Available === | ===Status: Available === | ||
: Looking for 1-2 Semester/Master students | : Looking for 1-2 Semester/Master students | ||
Revision as of 16:48, 26 March 2014
Contents
Short Description
In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the receiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver.
The goal of this project is to design the digital transmitter and implement it either as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and finally measured during the VLSI III lecture.
Status: Available
- Looking for 1-2 Semester/Master students
- Contact: Sandro Belfanti
Prerequisites
- VLSI I
- MATLAB and VHDL is an advantage
- Interest in Mobile Communications
Character
- 20% Theory/MATLAB
- 30% VHDL
- 50% Implementation
