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This project will give you insight into all parts of a modern 3G standard, such a coding, rate-matching, mapping and the digital frontend.
 
This project will give you insight into all parts of a modern 3G standard, such a coding, rate-matching, mapping and the digital frontend.
  
===Status: Available ===
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===Status: Completed ===
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: Looking for 1-2 Semester/Master students
 
: Looking for 1-2 Semester/Master students
 
: Contact: [[:User:Belfanti | Sandro Belfanti]]
 
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===Prerequisites===
 
===Prerequisites===
 
: VLSI I
 
: VLSI I
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===Professor===
 
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<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] --->
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[http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang]
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
  
 
[[Category:Digital]]
 
[[Category:Digital]]
 
[[Category:FPGA]]
 
[[Category:FPGA]]
[[Category:ASIC]]
 
 
[[Category:System Design]]
 
[[Category:System Design]]
 
[[Category:Telecommunications]]
 
[[Category:Telecommunications]]
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[[Category:Semester Thesis]]
 
[[Category:Semester Thesis]]
[[Category:Master Thesis]]
 
 
[[Category:Belfanti]]
 
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Latest revision as of 19:00, 26 September 2017

Creating Transmitter and Testbed Development for TD-SCDMA.jpg

Short Description

In this project you get the chance to develop and test a transmitter for a 3G mobile communications system. The IIS is currently working on a receiver for TD-HSPA, a 3G standard emerging from China. In order to complete the transceiver a high-speed uplink packet access (HSUPA) transmitter will be realized in VHDL during this thesis. The transmitter takes the raw data and takes care of putting it in a TD-HSPA compliant frame structure, applies the error correction coding and rate-matching and finally maps the digital '0's and '1's to physical I/Q symbols which can then be forwarded to an analog transceiver.

The goal of this project is to design the digital transmitter and implement it either as an ASIC or on a FPGA board, depending on your preferences. In case of a design project, the final transmitter can then be taped out, manufactured and finally measured during the VLSI III lecture. For an implementation on an FPGA, the resulting system (combined with the existing analog transceiver) can be tested using a protocol tester and you will then be able to actually send data over the air.

This project will give you insight into all parts of a modern 3G standard, such a coding, rate-matching, mapping and the digital frontend.

Status: Completed

Prerequisites

VLSI I
MATLAB and VHDL is an advantage
Interest in Mobile Communications

Character

20% Theory/MATLAB
30% VHDL
50% Implementation

Professor

Qiuting Huang