Energy Efficient AXI Interface to Serial Link Physical Layer

Overview

Status: Available

Looking for semester project

Supervisor:

• • Tim Fischer: fischeti@iis.ee.ethz.ch
  • Sina Arjmandpour: sarjmandpour@iis.ee.ethz.ch

Project

Designing and implementing an energy-efficient AXI (Advanced eXtensible Interface) interface with a serial link physical layer involves developing a high-speed communication system that provides a standardized and efficient interface between different IP blocks with minimal power consumption. The project requires expertise in digital circuit design, communication protocols, as well as power management techniques. The project goal is to integrate the AXI interface with a serial link physical layer to enable high-speed communication between IP blocks with minimal power consumption. This involves selecting an appropriate protocol anf developing a suitable circuit architecture that incorporates the AXI interface and serial link physical layer, and implementing power-saving techniques such as voltage scaling, clock gating, and data compression. The project will require simulation and testing of the system to verify its performance, power consumption, and compatibility with different IP blocks. The final deliverable is an energy-efficient AXI interface with serial link physical layer that meets the specified data rate, power consumption, and compatibility requirements.

Prerequisites

• Experience with System Verilog or Verilog, VLSI 1
• Experience with physical implementation, VLSI 2

Character

• 20% System Integration
• 20% Verification
• 30% Low-level software and drivers
• 30% Backend implementation

Professor

• Prof. Dr. Luca Benini
• Prof. Dr. Taekwang Jang