Difference between revisions of "Energy Efficient Circuits and IoT Systems Group"
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| + | rect 0 1101 1125 0 [[Design of key building blocks for miniaturized sensor systems]] | ||
| + | rect 1140 1101 2255 0 [[Energy Efficient Circuits for Wireless Neural Recording]] | ||
| + | rect 2278 1101 3418 0 [[Application Specific Frequency Synthesizers (Analog/Digital PLLs)]] | ||
| + | default [[Energy Efficient Circuits and IoT Systems Group]] | ||
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| + | </imagemap> | ||
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| + | ==Available Projects== | ||
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| + | category = Available | ||
| + | category = EECIS | ||
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| + | ==Active Projects== | ||
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| + | category = In progress | ||
| + | category = EECIS | ||
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| + | <DynamicPageList> | ||
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| + | category = In progress | ||
| + | category = Telecommunications | ||
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| + | ==Completed Projects== | ||
Revision as of 15:24, 25 September 2019
Available Projects
- Neural Recording Interface and Spike Sorting Algorithm
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Design of Streaming Data Platform for High-Speed ADC Data
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Energy Efficient Serial Link
- Design of low mismatch DAC used for VAD
- Development of an implantable Force sensor for orthopedic applications
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
Active Projects
- ASIC Development of 5G-NR LDPC Decoder
- Channel Estimation for 5G Cellular IoT and Fast Fading Channels
