Difference between revisions of "Energy Efficient Circuits and IoT Systems Group"
From iis-projects
(→Active Projects) |
|||
| (3 intermediate revisions by 2 users not shown) | |||
| Line 25: | Line 25: | ||
</DynamicPageList> | </DynamicPageList> | ||
| + | ==Completed Projects== | ||
| − | + | <DynamicPageList> | |
| + | category = Completed | ||
| + | category = EECIS | ||
| + | </DynamicPageList> | ||
Revision as of 11:06, 21 February 2022
Available Projects
- Neural Recording Interface and Spike Sorting Algorithm
- Energy-Efficient Edge-Pursuit comparator for ultra-low power ADC
- Design of Streaming Data Platform for High-Speed ADC Data
- Design of Power-Noise-Efficient Discrete-Time Amplifier Using Open-Source Tools
- An Ultra-Low-Power Neuromorphic Spiking Neuron Design
- Energy Efficient Serial Link
- Design of low mismatch DAC used for VAD
- Development of an implantable Force sensor for orthopedic applications
- Energy-efficient Circuits for Fully Wireless Brain-machine Interfaces
- Design of Time-Encoded Spiking Neural Networks (IBM-Zurich)
- Spiking Neural Network for Motor Function Decoding Based on Neural Dust
- Hardware/software codesign neural decoding algorithm for “neural dust”
- Exploring feature selection and classification algorithms for ultra-low-power closed-loop systems for epilepsy control
- Application Specific Frequency Synthesizers (Analog/Digital PLLs)
Active Projects
Completed Projects
- Optimal routing for 2D Mesh-based Analog Compute-In-Memory Accelerator Architecture (IBM-Zurich)
- Design of MEMs Sensor Interface
- Precise Ultra-low-power Timer
- Novel Metastability Mitigation Technique
- Analog Compute-in-Memory Accelerator Interface and Integration
- Low-power Temperature-insensitive Timer
- Exploring features and algorithms for ultra-low-power closed-loop systems for epilepsy control
