Difference between revisions of "Energy Efficient SoCs"
From iis-projects
(Created page with "<!-- File:NVIDIA Tesla V100.jpg|small|right|A NVIDIA Tesla V100 GP-GPU. This cutting-edge accelerator provides huge computational power on a [https://arstechnica.com/gadge...") |
|||
Line 7: | Line 7: | ||
Energy Efficient Systems on Chip are one of the group's flagship research topics. With an increasing demand for near-sensor processing, the energy-boundedness of embedded IoT devices becomes an issue. The goal of this particular research field is to come up with new architecture for high-performance heterogeneous compute platforms that push the limits of energy-efficiency for digital signal processing and embedded machine learning applications. Under the brand PULP (parallel ultra low power) we are actively developing several single and multi-core RISC-V SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators. | Energy Efficient Systems on Chip are one of the group's flagship research topics. With an increasing demand for near-sensor processing, the energy-boundedness of embedded IoT devices becomes an issue. The goal of this particular research field is to come up with new architecture for high-performance heterogeneous compute platforms that push the limits of energy-efficiency for digital signal processing and embedded machine learning applications. Under the brand PULP (parallel ultra low power) we are actively developing several single and multi-core RISC-V SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators. | ||
− | As part of our research activities we regularly tape-out PULP based SoC in various sizes, from smaller student tape-outs incorporating novel hardware accelerators to larger multi-cluster SoCs. On [https://www.pulp-platform. | + | As part of our research activities we regularly tape-out PULP based SoC in various sizes, from smaller student tape-outs incorporating novel hardware accelerators to larger multi-cluster SoCs. On [https://www.pulp-platform.org] you will find more details about this particular research aspect of the digital circuits group. |
Revision as of 15:52, 16 November 2020
Energy Efficient Systems on Chip are one of the group's flagship research topics. With an increasing demand for near-sensor processing, the energy-boundedness of embedded IoT devices becomes an issue. The goal of this particular research field is to come up with new architecture for high-performance heterogeneous compute platforms that push the limits of energy-efficiency for digital signal processing and embedded machine learning applications. Under the brand PULP (parallel ultra low power) we are actively developing several single and multi-core RISC-V SoC architectures that combine the versatility of parallel general-purpose computing with the energy efficiency of application-specific hardware accelerators.
As part of our research activities we regularly tape-out PULP based SoC in various sizes, from smaller student tape-outs incorporating novel hardware accelerators to larger multi-cluster SoCs. On [1] you will find more details about this particular research aspect of the digital circuits group.
Contents
Manuel Eggimann
- e-mail:meggiman@iis.ee.ethz.ch
- phone: +41 44 632 99 58
- office: ETZ J68
Alfio Di Mauro
- e-mail:adimauro@iis.ee.ethz.ch
- office: ETZ J78
Robert Balas
- e-mail:balasr@iis.ee.ethz.ch
- office: ETZ J78
Projects Overview
Available Projects
- Extending our FPU with Internal High-Precision Accumulation (M)
- Low Precision Ara for ML
- Hardware Exploration of Shared-Exponent MiniFloats (M)
- Approximate Matrix Multiplication based Hardware Accelerator to achieve the next 10x in Energy Efficiency: Full System Intregration
- Extended Verification for Ara
- Ibex: Tightly-Coupled Accelerators and ISA Extensions
- RVfplib
- Scalable Heterogeneous L1 Memory Interconnect for Smart Accelerator Coupling in Ultra-Low Power Multicores
Projects In Progress