Enhancing Our DMA Engine With Virtual Memory (M/1-3S/B)

Overview

Status: Available

• Type: Bachelor / Semester Thesis or Group Project
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Thomas Benz: tbenz@iis.ee.ethz.ch

Introduction

At IIS we are developing a scalable and flexible family of DMA engines called iDMA. So far our DMA engine works on physical memory only, requiring either the processor to do the PM/VM translation or relying on an external IOMMU (IO Memory Management Unit).

We have developed a minimal hardware PTW (page table walker) compliant with the RISC-V specification and we have already started to integrate it into the iDMA architecture.

Project

In this project, you will finish the integration of the PTW into the iDMA in the form of a modular midend. There are still multiple challenges to solve in the process (huge pages, PTW manager interface integration, programming model, error handling, ...). After completing the hardware, the unit has to be verified and fully characterized (performance, hardware overhead, power, ...).

Character

• 20% Getting familiar with the RISC-V spec, our PTW, and the iDMA
• 30% Design and implementation of the VM midend
• 20% Driver implementation, benchmarking
• 30% Verification and evaluation OOC and in-system

Prerequisites

• Interest in memory systems
• Experience with digital design in SystemVerilog as taught in VLSI I
• Preferred: Knowledge of AXI4