View source for Evaluating The Use of Snitch In The PsPIN RISC-V In-network Accelerator (M)

[[Category:Digital]]
[[Category:High Performance SoCs]]
[[Category:Computer Architecture]]
[[Category:FPGA]]
[[Category:2023]]
[[Category:Master Thesis]]
[[Category:Tbenz]]
[[Category:Available]]


== Status: Available ==

* Professor: Prof. Dr. L. Benini
* Supervisors:
** [[:User:Tbenz | Thomas Benz]]: [mailto:tbenz@iis.ee.ethz.ch tbenz@iis.ee.ethz.ch]

== Introduction ==
The SPCL group is working on PsPIN [1], an implementation of the sPIN programming model [2] based on PULP [3] for energy-efficient flexible high-performance in-network packet processing. So far we have used the traditional PULP cluster to perform the calculations. We would now investigate if package processing could further be accelerated if we are using the Snitch [4] infrastructure.


= Project =
In this project, you will update the PULP implementation of sPIN (PsPIN) to the newest version of the PULP cluster. You then integrate Snitch, creating SsPIN in te process. Finally, you will evaluate the advantages and disadvantages of either implementation on an FPGA.

== Character ==

* 20% Getting used to PsPIN and updating the PULP cluster to the most recent version
* 40% Implementing Snitch, creating SsPIN
* 40% Evaluating both versions, comparing them quantitatively

== Prerequisites ==

* Interest in memory systems
* Experience with digital design in SystemVerilog as taught in VLSI I

= References =

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<div id="ref-pspin">
[1] “Di Girolamo Salvatore, Kurth Andreas, Calotoiu Alexandru, Benz Thomas, Schneider Timo, Beranek Jakub, Benini Luca, Hoefler Torsten. "A RISC-V in-network accelerator for flexible high-performance low-power packet processing." 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2021..” https://ieeexplore.ieee.org/iel7/12/9821023/09522037.pdf
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<div id="ref-spin>
[2] Hoefler Torsten, Salvatore Di Girolamo, Konstantin Taranov, Ryan E. Grant, and Ron Brightwell. "sPIN: High-performance streaming Processing in the Network." In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, pp. 1-16. 2017.
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<div id="ref-pulp">
[3] Rossi, Davide, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, and Luca Benini. "PULP: A parallel ultra-low power platform for next generation IoT applications." In 2015 IEEE Hot Chips 27 Symposium (HCS), pp. 1-39. IEEE, 2015.
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<div id="ref-snitch">
[4] F. Zaruba, F. Schuiki, T. Hoefler, and L. Benini, “Snitch: A 10 kGE Pseudo Dual-Issue Processor for Area and Energy Efficient Execution of Floating-Point Intensive Workloads.” 2020.
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