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Difference between revisions of "Evaluating the RiscV Architecture"

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(Short Description)
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==Short Description==
 
==Short Description==
 
At the IIS we are working on a new family of ultra low power processors
 
At the IIS we are working on a new family of ultra low power processors
called [[PULP]] (Parallel Ultra Low Powwer Platform). Our current designs are based on
+
called [[PULP]] (Parallel Ultra Low Power Platform). Our current designs are based on
 
the or1k core from the [http://opencores.org/or1k opencores project]. We have modified this core
 
the or1k core from the [http://opencores.org/or1k opencores project]. We have modified this core
 
significantly and call the new core [[Ultra-low_power_processor_design|or10n]]. The  
 
significantly and call the new core [[Ultra-low_power_processor_design|or10n]]. The  

Revision as of 10:55, 5 February 2015

RiscV.jpg

Short Description

At the IIS we are working on a new family of ultra low power processors called PULP (Parallel Ultra Low Power Platform). Our current designs are based on the or1k core from the opencores project. We have modified this core significantly and call the new core or10n. The Risc V is another new micro-architecture designed by the Computer Science Department of University of California Berkeley.

In this work we would like to compare the performance of both cores in the PULP environment. As part of the project, you will adapt and implement a small Risc V compliant core, replace the or10n cores in a small PULP cluster with this new core and run an extensive set of comparisons. We would like to know how the cores compare in all performance aspects (area/ speed / power/ code size etc.) The plan is to manufacture the Risc V based PULP cluster in UMC 65nm technology, to obtain also measurement results.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Frank K. Gürkaynak
Antonio Pullini

Prerequisites

VLSI I
VLSI II (recommended)

Character

20% Theory
40% ASIC Design
40% EDA tools

Professor

Luca Benini

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