Exploitation of Inherent Error Resilience of Wireless Systems under Unreliable Silicon
- Christoph Roth
- Christian Benkeser
- Georgios Karakonstantis (EPFL)
- Andreas Burg (EPFL)
Memories are particularly susceptible to process variations that come along with modern semiconductor process technologies. In order to ensure 100% reliable operation, error-correction schemes are required that are costly in terms of silicon area- and power overhead. In addition, the application of effective low-power techniques (e.g., aggressive voltage scaling) makes the fabricated circuits even more prone to process variations. Consequently, realizing cost-effective and energy-efficient integrated circuits in the future requires a paradigm shift from the assumption of 100% reliable computing to fault-tolerant systems. This is especially important for wireless communication systems, where memories are dominating both silicon area and power consumption already today. In this work, we have investigated the impact of memory failures on the performance and yield of wireless communication systems using the 3GPP TD-HSPA standard as a test vehicle. We have focused on the large memory required for the hybrid-ARQ operation that is critical for the average throughput performance of the system.
Our study has revealed that the considered system shows an inherent resilience to memory failures and works within the specs of the standard up to very high defect rates. Furthermore, we have devised a new storage scheme where the MSBs of the stored receive values are protected and the other bits left unprotected. This approach further increases the resilience of the system, at an area overhead that is still significantly lower than the one required to ensure 100%reliable operation.
- G. Karakonstantis, C. Roth, C. Benkeser, A. Burg, "On the Exploitation of the Inherent Error Resilience of Wireless Systems under Unreliable Silicon", 49th ACM/EDAC/IEEE Design Automation Conference (DAC), San Francisco, California, USA, 3-7 Jun 2012