Extended Verification for Ara
Vector processing is becoming a widespread option when dealing with highly parallel data workloads, thanks to its intrinsic computational capabilities and flexibility inherited from the Cray-1 processor. For example, “FUGAKU”, the most performant supercomputer in the world, is a vector processor!
A vector core can sustain high computational throughput using deep pipelines and multiple parallel units and, unlike standard SIMD architectures, can adjust the vector length at runtime without the need for new ISA instructions for different specific vector lengths.
What a time for a project on a vector processor! RISC-V has almost finished ratifying its open-source vector ISA RVV (a process that lasted many years!), and many industries/universities are producing their first RVV-compatible cores.
ETH is at the forefront of this race with its agile in-order vector processor Ara, fresh from an update from the unripe specifications RVV 0.5. Still, the processor is far from being exhaustively verified: this fact slows down the development and benchmarking effort since unknown bugs make large programs fail, with a consequent overly-large waste of time, trying to isolate the hidden problem.
Verification is one of the most time consuming aspects of a design (>55% of the total) , and it’s also one of the most important ones. Even though it’s a highly requested skill by companies, it is hardly explored in academic environments, where the research time pressure favors novelties and new ideas.
Project: Extended Verification for Ara
This project aims at extending Ara’s verification infrastructure.
Currently, Ara supports RVV1.0 with some minor exceptions. The design is verified in two ways:
- By extending the riscv_tests repository with vector macros and test cases. This means that, for each RISC-V supported instruction, there is a C program which tests some hand-written common/edge cases. The programs verify themselves by comparing results with golden values; to be sure that they are correct, they are run also with SPIKE, the RISC-V golden model.
- Empirically, by running more complex benchmarks and programs on the Ara system.
Throughout the project, you will extend this environment, helped by supervisors from ETH and from a company.
There are many ways to verify a digital design; one of them is to use random-constrained sequences of instructions generated automatically. OpenHW Group has developed a useful tool to accomplish so , and, luckily, it supports RVV1.0.
In the first instance, you will familiarize with Ara and then study and understand 1) OpenHW Group’s verification environment and 2) Force RISC-V instruction sequence generator.
Then, you will port our Vector Processor to OpenHW Group’s verification environment, and prepare a testing strategy to increase our processor’s reliability.
Verification is not only a useful skill per se, but forces you to understand completely how the design should work by making you face what does not. During the project, you will learn, with your supervisor, how to analyze and fix hidden issues in a complex and intriguing design.
- Strong interest and basic knowledge in computer architecture, both on the HW and SW sides
- Experience with SystemVerilog HDL, such as taught in VLSI I
- C programming language
- Bonus: Knowledge of ASIC tool flow (Synthesis + PnR), or parallel enrollment with VLSI II
- Bonus: being familiar with vector processors, RISC-V RVV
- Bonus: UVM
Composition: 20% Study, 10% RTL implementation, 20% verification strategy, 50% Verification
What will you learn
During the project, you will develop several skills.
- Understand how a Vector architecture works.
- Use git and cooperate on a complex project with companies.
- Learn different ways to verify non-trivial digital designs.
- Learn how to deal with a complex design and environment.
 Ara: https://arxiv.org/pdf/1906.00478.pdf
 Ara source code: https://github.com/pulp-platform/ara
 Cray-Processor: http://www.edwardbosworth.com/My5155_Slides/Chapter13/Cray_Supercomputers.htm