Extending Our DMA Architecture with SiFives TileLink Protocol (1-3S/B)
- Type: Bachelor / Semester Thesis
- Professor: Prof. Dr. L. Benini
TileLink (https://static.dev.sifive.com/docs/tilelink/tilelink-spec-1.7-draft.pdf) is a chip-scale interconnect standard providing multiple masters with coherent memory-mapped access to memory and other slave devices introduced by SiFive. At IIS, we are developing a modular DMA architecture based on ARM's AXI (Advanced eXtensible Interface) protocol. We would now like to extend our DMA to be compatible with the TileLink protocol.
You will extend our DMA with the TileLink protocol.
- 20% Study the TileLink protocol, understanding the DMA architecture
- 40% Design, implementation, and verification of the protocol layer
- 40% Evaluation and optimization of your implementation
- Interest in memory systems
- Experience with digital design in SystemVerilog as taught in VLSI I
- Preferred: Knowledge of AXI4