Personal tools

Difference between revisions of "FPGA-Based Digital Frontend for 3G Receivers"

From iis-projects

Jump to: navigation, search
(Professor)
 
Line 35: Line 35:
  
 
===Professor===
 
===Professor===
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/lbenini.en.html Luca Benini] --->
+
[http://www.iis.ee.ethz.ch/people/person-detail.html?persid=78758 Qiuting Huang]
: [http://www.iis.ee.ethz.ch/portrait/staff/huang.en.html Qiuting Huang]
 
<!-- : [http://lne.ee.ethz.ch/en/general-information/people/professor.html Vanessa Wood] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/mluisier.en.html Mathieu Luisier] --->
 
<!-- : [http://www.iis.ee.ethz.ch/portrait/staff/schenk.en.html Andreas Schenk] --->
 
<!-- : [http://www.dz.ee.ethz.ch/en/general-information/about/staff/uid/364.html Hubert Kaeslin] --->
 
  
 
[[Category:Digital]]
 
[[Category:Digital]]

Latest revision as of 19:01, 26 September 2017

Testbed.JPG

Short Description

A modern receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received data. In this project you will work on the very first digital block after the analog part. The received data has to be obtained from the analog frontend, filtered, down-sampled and non-idealities in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE). A complete model of the digital receiver without the DFE has already been developed at the IIS. In order to work with real data this DFE will be implemented on a FPGA-board, which is connected to an existing analog tranceiver. Your task will be to implement the DFE on an FPGA and verify the functionality together with the already existing parts. In the end, the complete chain will be able to receive data which was generated by a protocol tester, transmitted over the air through analog frontend your DFE and the IIS digital baseband receiver.

This project can either be varied and be done as either a semester or masters thesis.

Status: Completed

Prerequisites

VLSI I
MATLAB and VHDL is an advantage

Character

20% Theory/Simulation
50% VHDL
30% FPGA Implementation

Professor

Qiuting Huang