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FPGA-Based Digital Frontend for 3G Receivers

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Revision as of 10:58, 4 February 2015 by Belfanti (talk | contribs) (Links)
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Short Description

A modern receiver for 3G mobile communications standard, such as the ones present in any mobile phone, consist of many digital blocks which process the received data. In this project you will work on the very first digital block after the analog part. The received data has to be obtained from the analog frontend, filtered, down-sampled and non-idealities in the receiver, such as a DC-offset, have to be corrected. This is done in the Digital Frontend (DFE). A complete model of the digital receiver without the DFE has already been developed at the IIS. In order to work with real data this DFE will be implemented on a FPGA-board, which is connected to an existing analog tranceiver. Your task will be to implement the DFE on an FPGA and verify the functionality together with the already existing parts. In the end, the complete chain will be able to receive data which was generated by a protocol tester, transmitted over the air through analog frontend your DFE and the IIS digital baseband receiver.

This project can either be varied and be done as either a semester or masters thesis.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Sandro Belfanti


MATLAB and VHDL is an advantage


20% Theory/Simulation
50% VHDL
30% FPGA Implementation


Qiuting Huang

Detailed Task Description


Practical Details



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