Difference between revisions of "FPGA-based Testbed Implementation of an Extended-Coverage Point-to-Point Communication Link for the Internet of Things"
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Latest revision as of 12:54, 13 November 2020
The Internet of Things (IoT) will be one of the key drivers of the semiconductor industry in the upcoming years with a wide range of potential applications such as smart appliances, wearables, or autonomous driving. Smart drones will be another vital part of IoT with various use cases like parcel delivery or drone taxis. Although the latter one still sounds like science fiction today, in fact first drone taxis are being planned to operate in Dubai later this year. The novelty of all these use cases makes new communication protocols inevitable resulting in today’s IoT standardization efforts including cellular IoT (Extended-Coverage-GSM and Narrowband-IoT) and clean-slate standards like SigFox or LoRa that are completely optimized towards IoT. While all these standards base on a base-station-centric network topology, little effort is spent on point-to-point communication links targeting IoT today.
The proposed project is a start to fill this gap by setting up an FPGA-testbed environment and emulate a first extended-coverage point-to-point link. Thereby, a base-station-centric cellular-IoT testbed serves as a starting point which consists of a vector signal generator mimicking a cellular IoT base station, an integrated analog RF-transceiver, and an FPGA evaluation platform emulating the user-equipment’s digital baseband processing. As the uplink and downlink communication protocol differ in cellular standards, the first step in this project is to align receive and transmit parts of the digital baseband processing in order to enable a direct point-to-point communication link. In a second step, the communication protocol will be gradually optimized towards the point-to-point use case with the main focus on extended coverage and low power consumption. As the bigger part of the affected digital baseband processing is mapped to a RISC-V processor, most of the work throughout the project requires embedded C coding, with some work in HDL being required eventually.
- Looking for Interested Master Students (Semester Project / Master Thesis)
- Contact: Matthias Korb
- Knowledge in C/Cpp