Revision as of 14:50, 13 November 2023

Overview

Status: Available

• Type: Master Thesis
• Professor: Prof. Dr. L. Benini
• Supervisors:
  • Luca Bertaccini: lbertaccini@iis.ee.ethz.ch
  • Michael Rogenmoser: michaero@iis.ee.ethz.ch

Introduction

FPnew block diagram [1]. Each operation group block can be instantiated through a parameter. In the figure, the FPU was instantiated without a DivSqrt module.

Fault-tolerant features are crucial in critical and hostile environments (automotive, space, …). The goal of this project is to enhance the FP unit (FPU) developed at IIS [1] with fault-tolerant features (such as redundancy schemes [2]).

Character

• 20% Literature / architecture review
• 40% RTL implementation
• 40% Evaluation

Prerequisites

• Strong interest in computer architecture
• Experience with digital design in SystemVerilog as taught in VLSI I
• Experience with ASIC implementation flow (synthesis) as taught in VLSI II

References

[1] https://github.com/pulp-platform/cvfpu

[2] https://arxiv.org/abs/2303.08706