Fault Tolerance
From iis-projects
In environments such as space or particle accelerators, soft errors (i.e. correctable bitflips) caused by radiation are much more frequent. Adding elements such as Triple Modular Redundancy (TMR) or Error Correcting Codes (ECC) can detect and correct these errors, however they can induce a large overhead or are not always applicable in case data changes. Furthermore, for certain applications (e.g. handling imprecise data), fault tolerance is not always needed, or only partially beneficial.
We offer a variety of projects augmenting and extending the PULP platform for fault tolerance.
Contents
Contact Information
Michael Rogenmoser
- e-mail: michaero@iis.ee.ethz.ch
- ETZ J71.2
Projects
If you have any other project or ideas relating to fault tolerance, feel free to send Michael Rogenmoser an email or drop by his office to discuss possibilities.
Available Projects
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Fault-Tolerant Floating-Point Units (M)
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Scan Chain Fault Injection in a PULP SoC (1S)
- Reliability by Switching the Embedded ISA in Ibex (1-2S/B/1M)
- Implementation of a Cache Reliability Mechanism (1S/M)
- On-Board Software for PULP on a Satellite
- Enhancing our DMA Engine with Fault Tolerance
Projects In Progress
Completed Projects
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Implementing Configurable Dual-Core Redundancy
- Triple-Core PULPissimo
- Watchdog Timer for PULP
