File:Channel Decoding for TD-HSPA.png
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Channel_Decoding_for_TD-HSPA.png (631 × 517 pixels, file size: 300 KB, MIME type: image/png)
Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.
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Date/Time | Thumbnail | Dimensions | User | Comment | |
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current | 10:10, 4 February 2014 | 631 × 517 (300 KB) | Kgf (talk | contribs) | Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology. |
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