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  • (cur | prev) 10:10, 4 February 2014Kgf (talk | contribs). . (214 bytes) (+214). . (Top: High-level architecture of the channel decoding chain for the downlink terminal side of 3GPP TD-HSPA. Bottom: Layout of the fabricated turbo and Viterbi decoder prototypes integrated in 180 nm CMOS technology.)