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Fitting Power Consumption of an IP-based HLS Approach to Real Hardware (1-3S)

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Status: Reserved


Creating large SoCs fully by hand is a tedious and error-prone process. At IIS, we have developed Solder, a python-based framework that allows us to construct and configure large SoCs from a catalog of our highly-optimized IPs.

We are in the process of enhancing Solder to not only construct larger systems but also give the developer rapid feedback about key numbers of merit (performance, area, timing, power, ...) facilitating the design space exploration process.

The power consumption of a system usually is the most difficult figure of merit to acquire, as it usually has to be measured on (or at least correlated to) real silicon.


In this project:

  • you first identify a key set of parameterization options of a given IP that best reflects the influence of the parameters on power consumption.
  • you then create RTL instantiating this minimal set of parametrization options in a stimuli generation framework.
  • you create an ASIC from this hardware and tape it out.


  • 20% Evaluation
  • 20% RTL creation
  • 60% ASIC creation


  • Interest in memory systems (as the IP will be a DMA unit)
  • Experience with digital design in SystemVerilog as taught in VLSI I
  • Following (or have completed in a previous semester) VLSI II