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Design and Implementation of a Convolutional Neural Network Accelerator ASIC

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Revision as of 19:47, 6 December 2014 by Lukasc (talk | contribs) (Goals)
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Short Description

Imaging sensor networks, UAVs, smartphones, and other embedded computer vision systems require power-efficient, low-cost and high-speed implementations of synthetic vision systems capable of recognizing and classifying objects in a scene. Many popular algorithms in this area require the evaluations of multiple layers of filter banks. Almost all state-of-the-art synthetic vision systems are based on features extracted using multi-layer convolutional networks (ConvNets). When evaluating ConvNets, most of the time is spent performing the convolutions (80% to 90%). The focus of this work is on speeding up this step by creating an accelerator to perform this step faster and more power-efficient.

Status: In Progress

David Gschwend, Christoph Mayer, Samuel Willi
Supervision: Lukas Cavigelli, Beat Muheim
Date: Fall Semester 2014 (sem14h17, sem14h18, sem14h19)

Prerequisites

Knowledge of Matlab
Interest in video processing and VLSI design
VLSI 1 and enrolment in VLSI 2 is required
At least one student has to test the chip as part of the VLSI 3 lecture, if the ASIC should be manufactured.

Character

10% Theory / Literature Research
60% VLSI Architecture, Implementation & Verification
30% VLSI back-end Design

Professor

Luca Benini

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Detailed Task Description

Goals

Explore various architectures to perform the 2D convolutions used in convolutional networks, considering the constraints of an ASIC design, and performing fixed-point analyses for the most viable architectures
Get to know the ASIC design flow from specification through architecture exploration to implementation, functional verification, back-end design and silicon testing.

Literature

Practical Details

Results

Links

The EDA wiki with lots of information on the ETHZ ASIC design flow (internal only) [[1]]


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