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Difference between revisions of "GSM Voice Capacity Evolution - VAMOS"

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===Prerequisites===
 
===Prerequisites===
: Interest in Mobile Communication
+
: Interest in mobile communication
 
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===Status: Completed ===
 
===Status: Completed ===

Revision as of 09:47, 6 February 2015

Vamos.png

Short Description

The GSM technology was originally designed for voice services only. GPRS and EDGE provide packet switched data on top of the existing GSM topology. However, data hungry devices such as smart phones require a lot of resources (time slots) on GSM carriers. Network operators face the challenge of providing sufficient Voice and packet switched connections simultaneously. The latest packet switched GSM enhancement called Evolved EDGE even allows 1 Mobile Station (MS) to use 2 frequency carriers in the downlink. This further provides less time slots available for Voice connections and, what's more, for emerging Machine-to-Machine (M2M) applications.

The latest remarkable GSM improvement is called VAMOS (Voice services over Adaptive Multi-user channels on One Slot). It virtually doubles Voice capacity of existing deployments without any performance degradation and is fully backwards compatible with legacy phones. More detailed, 2 voice connections are transmitted simultaneously on the same time slot. This results in 4 simultaneous voice connections if half rate voice codecs are used. The VAMOS enhancement essentially frees half of the currently used time slots for voice connections for M2M communication and other packet switched applications. This advantage, however, comes at a cost of more complex receiver structures.

In this work, the impact of VAMOS on an MS receiver shall be studied. A Matlab model for a VAMOS capable equalizer is development and eventually implemented in VHDL. Depending on the progress, an FPGA or ASIC design can be reached.

Status: Available

Looking for 1-2 Semester/Master students
Contact: Benjamin Weber

Prerequisites

Interest in mobile communication

Character

30% Theory
40% Matlab simulation
30% FPGA or ASIC design

Professor

Qiuting Huang