HW/SW Safety and Security
Real-Time Embedded Systems
A real-time computer system is a computer system in which the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical instant at which these results are produced.
In real-time systems, guarantees must be given on the finishing of computations before a deadline. This affects the design of hardware (processors, caches, interconnects, peripherals, interrupts, ...) and software stack (operating system, scheduling, compiler guarantees). Key concepts are spatial and temporal isolation of components, and architecture's predictability.
In short, high performance systems optimize for the average-case scenario, while predictable systems optimize for worst-case scenario.
One trend in real-time systems is to fuse regular low priority application code with real-time tasks on the same platform. This combination is called a Mixed Criticality System (MCS). For achieving this kind of design, various hardware and software pieces need to work together to ensure proper isolation of programs through virtualization, bandwidth partitioning, smart cahing etc. We are building such a system and offer various projects working on it.
Please continue to Cryptography if you are interested in cryptographic hardware.
Please continue to Fault Tolerance if you are interested in circuits tolerant to radiation-induced soft errors.
Who are we
All projects are annotated with one or more possible project types (M/S/B/G) and a number of students (1 to 3).
- M: Master's thesis: 26 weeks full-time (6 months) for one student only
- S: Semester project: 14 weeks half-time (1 semester lecture period) or 7 weeks full-time for 1-3 students
- B: Bachelor's thesis: 14 weeks half-time (1 semester lecture period) for one student only
- G: Group project: 14 weeks part-time (1 semester lecture period) for 2-3 students
Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- Non-blocking Algorithms in Real-Time Operating Systems
- PULP Freertos with LLVM
- Radiation Testing of a PULP ASIC
- Resource Partitioning of Caches
- Resource Partitioning of RPC DRAM
- Securing Block Ciphers against SCA and SIFA
- Zephyr RTOS on PULP
Projects In Progress
- Development of statistics and contention monitoring unit for PULP
- Implementing Configurable Dual-Core Redundancy