HW/SW Safety and Security
Real-Time Embedded Systems
A real-time computer system is a computer system in which the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical instant at which these results are produced. In fact, a real-time system changes its state as a function of physical time.
The instant at which a result of a computation must be produced is called a deadline. If a result has utility even after the deadline has passed, the deadline is classified as a soft deadline, otherwise it is a firm deadline. When missing a firm deadline results in a system failure (e.g. airplane sensor and autopilot systems, spacecrafts and planetary rovers), the deadline is called hard deadline.
Hence, in real-time systems guarantees must be given on the finishing of computations before a deadline. This affects the design of hardware (processors, caches, interconnects, peripherals, interrupts, ...) and software stack (operating system, scheduling, compiler guarantees). Key concepts are spatial and temporal isolation of components, and architecture's predictability.
Please continue to Cryptography if you are interested in cryptographic hardware.
Please continue to Fault Tolerance if you are interested in circuits tolerant to radiation-induced soft errors.
Who are we
All projects are annotated with one or more possible project types (M/S/B/G) and a number of students (1 to 3).
- M: Master's thesis: 26 weeks full-time (6 months) for one student only
- S: Semester project: 14 weeks half-time (1 semester lecture period) or 7 weeks full-time for 1-3 students
- B: Bachelor's thesis: 14 weeks half-time (1 semester lecture period) for one student only
- G: Group project: 14 weeks part-time (1 semester lecture period) for 2-3 students
Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.
- CLIC for the CVA6
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- Integration and Implementation of Alibaba’s T-Head CLIC Interrupt Controller in PULP SoC
- Non-blocking Algorithms in Real-Time Operating Systems
- SCMI Support for Power Controller Subsystem
- Securing Block Ciphers against SCA and SIFA
- Watchdog Timer for PULP
Projects In Progress