Difference between revisions of "HW/SW Safety and Security"

Latest revision as of 20:08, 20 January 2022

Real-Time Embedded Systems

Control PULP is a research platform for testing and implementing real-time hardware concepts. It couples a RISC-V controller core with a cluster of eight RISC-V cores used as accelerator for various control intensive applications in this case a control loop involving thermal and power capping of HPC compute cores.

A real-time computer system is a computer system in which the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical instant at which these results are produced. In fact, a real-time system changes its state as a function of physical time.

The instant at which a result of a computation must be produced is called a deadline. If a result has utility even after the deadline has passed, the deadline is classified as a soft deadline, otherwise it is a firm deadline. When missing a firm deadline results in a system failure (e.g. airplane sensor and autopilot systems, spacecrafts and planetary rovers), the deadline is called hard deadline.

Hence, in real-time systems guarantees must be given on the finishing of computations before a deadline. This affects the design of hardware (processors, caches, interconnects, peripherals, interrupts, ...) and software stack (operating system, scheduling, compiler guarantees). Key concepts are spatial and temporal isolation of components, and architecture's predictability.

Cryptography

Please continue to Cryptography if you are interested in cryptographic hardware.

Fault Tolerance

Please continue to Fault Tolerance if you are interested in circuits tolerant to radiation-induced soft errors.

Who are we

Robert Balas e-mail: balasr@iis.ee.ethz.ch phone: +41 44 632 42 56 office: ETZ J78

Alessandro Ottaviano e-mail: aottaviano@iis.ee.ethz.ch phone: +41 44 632 57 45 office: ETZ J89

Michael Rogenmoser e-mail: michaero@iis.ee.ethz.ch phone: +41 44 632 54 33 office: ETZ J71.2

Nils Wistoff e-mail: nwistoff@iis.ee.ethz.ch phone: +41 44 632 06 75 office: ETZ J85

Projects

All projects are annotated with one or more possible project types (M/S/B/G) and a number of students (1 to 3).

• M: Master's thesis: 26 weeks full-time (6 months) for one student only
• S: Semester project: 14 weeks half-time (1 semester lecture period) or 7 weeks full-time for 1-3 students
• B: Bachelor's thesis: 14 weeks half-time (1 semester lecture period) for one student only
• G: Group project: 14 weeks part-time (1 semester lecture period) for 2-3 students

Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.

Available Projects

• CLIC for the CVA6
• Enhancing our DMA Engine with Fault Tolerance
• Fast Accelerator Context Switch for PULP
• Non-blocking Algorithms in Real-Time Operating Systems
• SCMI Support for Power Controller Subsystem
• Securing Block Ciphers against SCA and SIFA

Projects In Progress

• Hypervisor Extension for Ariane (M)
• PULP’s CLIC extensions for fast interrupt handling

• Triple-Core PULPissimo
• Watchdog Timer for PULP

Completed Projects

• Securing Block Ciphers against SCA and SIFA