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We are in the processes of creating a top-level information page, in the meantime please continue directly to the specific subsections below.
 
  
== Real-Time Embedded Systems ==
 
Please continue to [[Real-Time Embedded Systems]] if you are interested in designing hardware or writing software for timing predictable embedded systems.
 
 
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== Predictable Execution ==
 
== Predictable Execution ==
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Please continue to [[Predictable_Execution]] if you are interested in timing predictable/safety critical embedded systems.  
 
Please continue to [[Predictable_Execution]] if you are interested in timing predictable/safety critical embedded systems.  
 
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== Real-Time Embedded Systems ==
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Please continue to [[Real-Time Embedded Systems]] if you are interested in designing hardware or writing software for timing predictable embedded systems.
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[[File:Control_PULP_with_CLIC.png|thumb|350px|''Control PULP'' is a research platform for testing and implementing real-time hardware concepts. It couples a RISC-V controller core with a cluster of eight RISC-V cores used as accelerator for various control intensive applications in this case a control loop involving thermal and power capping of HPC compute cores.]]
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A real-time computer system is a computer system in which the correctness of the system behavior depends not only on the '''logical results''' of the computations, but also on the '''physical instant''' at  which these results are produced. In fact, a real-time system changes its state as a function of physical time.
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The  instant  at  which  a  result of a computation must  be  produced  is  called  a  '''deadline'''. If  a  result  has  utility even after the deadline  has  passed, the deadline is classified as a '''soft deadline''', otherwise  it  is  a '''firm deadline'''. When missing a firm  deadline  results in a system failure (e.g. airplane sensor and autopilot systems, spacecrafts and planetary rovers), the deadline is called '''hard deadline'''.
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Hence, in real-time systems guarantees must be given on the finishing of computations before a deadline. This affects the design of hardware (processors, caches, interconnects, peripherals, interrupts, ...) and software stack (operating system, scheduling, compiler guarantees). Key concepts are '''spatial and temporal isolation''' of components, and ''' architecture's predictability'''.
  
 
== Cryptography ==
 
== Cryptography ==
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===[[:User:Balasr | Robert Balas]]===
 
===[[:User:Balasr | Robert Balas]]===
 
* '''e-mail''': [mailto:balasr@iis.ee.ethz.ch balasr@iis.ee.ethz.ch]
 
* '''e-mail''': [mailto:balasr@iis.ee.ethz.ch balasr@iis.ee.ethz.ch]
* '''phone''': +41 44 632 42 5
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* '''phone''': +41 44 632 42 56
* '''office''': ETZ J85
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* '''office''': ETZ J78
 
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===Projects In Progress===
 
===Projects In Progress===
 
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category = Reserved
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category = Digital
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category = Fault Tolerance
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===Completed Projects===
 
===Completed Projects===
 
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Revision as of 16:45, 10 January 2022

Real-Time Embedded Systems

Control PULP is a research platform for testing and implementing real-time hardware concepts. It couples a RISC-V controller core with a cluster of eight RISC-V cores used as accelerator for various control intensive applications in this case a control loop involving thermal and power capping of HPC compute cores.

A real-time computer system is a computer system in which the correctness of the system behavior depends not only on the logical results of the computations, but also on the physical instant at which these results are produced. In fact, a real-time system changes its state as a function of physical time.

The instant at which a result of a computation must be produced is called a deadline. If a result has utility even after the deadline has passed, the deadline is classified as a soft deadline, otherwise it is a firm deadline. When missing a firm deadline results in a system failure (e.g. airplane sensor and autopilot systems, spacecrafts and planetary rovers), the deadline is called hard deadline.

Hence, in real-time systems guarantees must be given on the finishing of computations before a deadline. This affects the design of hardware (processors, caches, interconnects, peripherals, interrupts, ...) and software stack (operating system, scheduling, compiler guarantees). Key concepts are spatial and temporal isolation of components, and architecture's predictability.

Cryptography

Please continue to Cryptography if you are interested in cryptographic hardware.

Fault Tolerance

Please continue to Fault Tolerance if you are interested in circuits tolerant to radiation-induced soft errors.

Who are we

Robert balas.jpeg

Robert Balas

Aottaviano.jpg

Alessandro Ottaviano

Michaero PULP.jpeg

Michael Rogenmoser

Nwistoff face pulp team.JPG

Nils Wistoff


Projects

All projects are annotated with one or more possible project types (M/S/B/G) and a number of students (1 to 3).

  • M: Master's thesis: 26 weeks full-time (6 months) for one student only
  • S: Semester project: 14 weeks half-time (1 semester lecture period) or 7 weeks full-time for 1-3 students
  • B: Bachelor's thesis: 14 weeks half-time (1 semester lecture period) for one student only
  • G: Group project: 14 weeks part-time (1 semester lecture period) for 2-3 students

Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.

Available Projects

Projects In Progress

Completed Projects