HW/SW Safety and Security
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Revision as of 10:38, 6 January 2022 by Aottaviano (talk | contribs)
We are in the processes of creating a top-level information page, in the meantime please continue directly to the specific subsections below.
Contents
Real-Time Embedded Systems
Please continue to Real-Time Embedded Systems if you are interested in designing hardware or writing software for timing predictable embedded systems.
Cryptography
Please continue to Cryptography if you are interested in cryptographic hardware.
Fault Tolerance
Please continue to Fault Tolerance if you are interested in circuits tolerant to radiation-induced soft errors.
Who are we
Robert Balas
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Alessandro Ottaviano
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Michael Rogenmoser
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Nils Wistoff
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Projects
All projects are annotated with one or more possible project types (M/S/B/G) and a number of students (1 to 3).
- M: Master's thesis: 26 weeks full-time (6 months) for one student only
- S: Semester project: 14 weeks half-time (1 semester lecture period) or 7 weeks full-time for 1-3 students
- B: Bachelor's thesis: 14 weeks half-time (1 semester lecture period) for one student only
- G: Group project: 14 weeks part-time (1 semester lecture period) for 2-3 students
Usually, these are merely suggestions from our side; proposals can often be reformulated to fit students' needs.
Available Projects
- Designing a Fault-Tolerant On-Chip Interconnect (1-2S/M)
- Enhancing our DMA Engine with Fault Tolerance
- Fast Accelerator Context Switch for PULP
- FPGA mapping of RPC DRAM
- Non-blocking Algorithms in Real-Time Operating Systems
- PULP Freertos with LLVM
- Resource Partitioning of RPC DRAM
- Scan Chain Fault Injection in a PULP SoC (1S)
- Securing Block Ciphers against SCA and SIFA
Projects In Progress
- A RISC-V fault-tolerant many-core accelerator for 5G Non-Terrestrial Networks (1-2S/B)
- Fault-Tolerant Floating-Point Units (M)
- Implementation of a Cache Reliability Mechanism (1S/M)
- On-Board Software for PULP on a Satellite
- Radiation Testing of a PULP ASIC
- Zephyr RTOS on PULP
Completed Projects
- Resource Partitioning of Caches
- Design of an Area-Optimized Soft-Error Resilient Processing Core for Safety-Critical Systems (1M)
- Development of statistics and contention monitoring unit for PULP
- Implementing Configurable Dual-Core Redundancy
- Peripheral Event Linking System for Real-time Capable Energy Efficient SoCs
- CLIC for the CVA6
- SCMI Support for Power Controller Subsystem
- PULP’s CLIC extensions for fast interrupt handling
- Triple-Core PULPissimo
- Watchdog Timer for PULP
- Hypervisor Extension for Ariane (M)
- Securing Block Ciphers against SCA and SIFA