Your mobile phone has one  , your ultrabook has one , and they may soon diffuse into data centers as well : Heterogeneous systems on chip are currently one of the main drivers for performance-per-energy advancements in various application domains. At their heart, these architectures combine general-purpose computing with domain-specific processing capabilities.
While this approach has the potential to bring unprecedented computing possibilities to various application domains, fundamental problems have to be solved to make heterogeneous SoCs truly ubiquitous. Most importantly, designing and programming heterogeneous SoCs to exploit their theoretical potential is challenging due to the high overall system complexity.
To be able to investigate these problems, we have built the Heterogeneous Embedded Research Platform (HERO). HERO combines an ARM Cortex-A host processor with a scalable, configurable, and extensible FPGA implementation of a programmable manycore accelerator (also developed in our group as part of the PULP project). Along its unique hardware combination, HERO features a heterogeneous software stack that supports OpenMP 4.5 and Shared Virtual Memory (SVM) for transparent accelerator programming. Parts of HERO are being and have been taped out on ASICs.
In the context of this research platform, we offer projects across the entire hardware/software stack. This is your chance to explore and work on (almost) any layer of a running computer system and contribute to energy-efficient next-generation computing platforms! We are currently looking for students to work on the projects below, but are also open to discuss suggestions from you. Please contact us if you are interested!
- e-mail: email@example.com
- ETZ J69.2
- e-mail: firstname.lastname@example.org
- ETZ J68.2
Projects In Progress
- Implementation of a Small and Energy-Efficient RISC-V-based Vector Accelerator (1M)
- Efficient Synchronization of Manycore Systems (M/1S)
- Transforming MemPool into a CGRA (M)
- Ottocore: A Minimal RISC-V Core Designed for Teaching (B/2G)
- LLVM and DaCe for Snitch (1-2S)
- Bringup and Evaluation of an Energy-efficient Heterogeneous Manycore Compute Platform (1-2S)
- A Snitch-Based SoC on iCE40 FPGAs (1-2S/B)
- ISA extensions in the Snitch Processor for Signal Processing (M)
- A Snitch-based Compute Accelerator for HERO (M/1-2S)
- MemPool on HERO (1S)
- Implementation of a Heterogeneous System for Image Processing on an FPGA (S)
- HERO: TLB Invalidation
- BigPULP: Shared Virtual Memory Multicluster Extensions
- BigPULP: Multicluster Synchronization Extensions
- Smart Virtual Memory Sharing
- PULPonFPGA: Lightweight Virtual Memory Support - Page Table Walker
- PULPonFPGA: Lightweight Virtual Memory Support - Multi-Level TLB
- PULPonFPGA: Lightweight Virtual Memory Support - Coherency Extensions