High-Resolution, Calibrated Folding ADCs
- ETH Zurich
Modern sub-micron CMOS technologies with reduced supply voltages target multi-gigahertz switching speeds for highly accelerated digital signal processing in communications, multimedia, and other consumer electronics. To fulfill the performance requirements in today’s consumer electronics, the demand for A/D converters (ADCs) with medium resolutions (10-12 bits) and sampling rates in excess of 100 MS/s is increasing. Folding ADCs provide high-bandwidth, medium resolution, and a reduced number of comparators with respect to generic flash ADCs. Folding architectures employ a parallel architecture consisting of open-loop folding amplifiers to reach high conversion rates. A drawback of the folding architecture is its limited accuracy, which is directly related to transistor matching in the employed folding amplifiers. Device mismatch induces a large input offset voltage which result in a non-linear transfer characteristic and thus loss in ENOB. Averaging is a promising approach to alleviate the matching requirements and calibration techniques can be applied to compensate for static non-linearity errors.
A 150-MS/s 11-bit digitally-calibrated folding ADC with a differential input voltage range of 1 Vpp prototyped in 130-nm CMOS is developed in this project. A new start-up calibration is applied to compensate for static non-linearity errors which limit the ADC’s precision. The start-up calibration deploys an area-efficient switched-capacitor integrator as a reference source to provide calibration vectors required in the static non-linearity correction algorithm. The correction algorithm improves the ADC’s precision while enhancing the SNDR and SFDR by around 15 dB and 20 dB, respectively. The ADC delivers 9.6 ENOB at low and 9.1 ENOB at Nyquist frequency, consuming 287 mW from a 1.2-V supply while occupying 1.74 mm2. The figure-of-merit (FoM) is 2.8 pJ/conversion while peak INL and DNL are 2.34 LSB and 1.56 LSB, respectively.